System, Apparatus And Method For Program Order Queue (POQ) To Manage Data Dependencies In Processor Having Multiple Instruction Queues

Patent metadata

Field	Value
Publication number	US-2020310815-A1
Application number	US-201916364688-A
Country	US
Kind code	A1
Filing date	Mar 26, 2019
Priority date	Mar 26, 2019
Publication date	Oct 1, 2020
Grant date	—

Abstract

In one embodiment, an apparatus includes: a plurality of registers; a first instruction queue to store first instructions; a second instruction queue to store second instructions; a program order queue having a plurality of portions each associated with one of the plurality of registers, each of the portions having entries to store a state of an instruction, the state comprising an encoding of a use of the register by the instruction and a source instruction queue for the instruction; and a dispatcher to dispatch for execution the first and second instructions from the first and second instruction queues based at least in part on information stored in the program order queue, to manage instruction dependencies between the first instructions and the second instructions. Other embodiments are described and claimed.

First claim

What is claimed is:

1 . An apparatus comprising:
a plurality of registers; a first instruction queue to store first instructions to be dispatched to one or more execution circuits; a second instruction queue to store second instructions to be dispatched to the one or more execution circuits; a program order queue having a plurality of portions each associated with one of the plurality of registers, each of the plurality of portions comprising a plurality of entries each to store a state of an instruction, the state comprising an encoding of a use of the register by the instruction and a source instruction queue for the instruction; and a dispatcher to dispatch for execution the first instructions from the first instruction queue and the second instructions from the second instruction queue based at least in part on information stored in the program order queue, to manage instruction dependencies between the first instructions and the second instructions.

2 . The apparatus of claim 1 , wherein the instruction dependencies include write-after-read dependencies, read-after-write dependencies and write-after-write dependencies.

3 . The apparatus of claim 1 , wherein for a first instruction of the first instructions having a first source operand that identifies a first register and a destination operand that identifies a second register, the program order queue is to store in a first portion of the program order queue associated with the first register a read event state and store in a second portion of the program order queue associated with the second register a write event state.

4 . The apparatus of claim 3 , wherein the read event state is to identify that the first instruction is stored in the first instruction queue.

5 . The apparatus of claim 3 , wherein the program order queue is to store the read event state and the write event state on allocation of the first instruction into the first instruction queue.

6 . The apparatus of claim 3 , wherein the dispatcher is to dispatch the first instruction from the first instruction queue to the one or more execution circuits when a top entry of the first portion of the program order queue includes the read event state and a top entry of the second portion of the program order queue includes the write event state.

7 . The apparatus of claim 6 , wherein the program order queue is to dequeue the top entry of the first portion of the program order queue when the first instruction is completed.

8 . The apparatus of claim 6 , wherein the dispatcher is to stall the first instruction in the first instruction queue when the top entry of the first portion of the program order queue does not include the read event state or the top entry of the second portion of the program order queue does not include the write event state.

9 . The apparatus of claim 1 , wherein for a first instruction of the first instructions having a first source operand that identifies a first register and a destination operand that identifies the first register, the program order queue is to store in a first portion of the program order queue associated with the first register a read write event state.

10 . The apparatus of claim 1 , wherein the apparatus comprises a single program multiple data processor including a plurality of execution lanes each including the one or more execution circuits, wherein each of the plurality of lanes is to execute instructions dispatched by the dispatcher.

11 . The apparatus of claim 1 , wherein the first instruction queue and the second instruction queue comprise in-order queues, the first instruction queue to store memory instructions and the second instruction queue to store arithmetic instructions.

12 . A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
receiving a first instruction for allocation into a first instruction queue of a processor, the first instruction identifying a first register as a first source operand and identifying a second register as a destination operand; enqueuing, into a first program order queue associated with the first register, a read event state that indicates that the first instruction is to read the first register and is allocated into the first instruction queue; enqueuing into a second program order queue associated with the second register, a write event state that indicates that the first instruction is to write the second register and is allocated into the first instruction queue; and controlling dispatch of the first instruction from the first instruction queue to at least one execution circuit based on contents of at least one entry of the first program order queue and at least one entry of the second program order queue.

13 . The machine-readable medium of claim 12 , wherein the method further comprises:
selecting the first instruction for dispatch to at least one execution circuit; determining whether a top entry of the first program order queue has the read event state that indicates that the first instruction is to read the first register and is allocated into the first instruction queue; and responsive, at least in part to determining that the top entry of the first program order queue has the read event state that indicates that the first instruction is to read the first register and is allocated into the first instruction queue, dispatching the first instruction to the at least one execution circuit.

14 . The machine-readable medium of claim 13 , wherein the method further comprises:
responsive to dispatching the first instruction to the at least one execution circuit, dequeuing the top entry of the first program order queue; and responsive to completion of the first instruction in the at least one execution circuit, dequeuing the top entry of the second program order queue.

15 . The machine-readable medium of claim 13 , wherein the method further comprises responsive to determining that the top entry of the first program order queue does not have the read event state that indicates that the first instruction is to read the first register and is allocated into the first instruction queue, stalling the first instruction in the first instruction queue.

16 . The machine-readable medium of claim 13 , wherein the method further comprises:
determining whether a top entry of the second program order queue has the write event state that that indicates that the first instruction is to write the second register and is allocated into the first instruction queue; and further responsive to determining that the top entry of the second program order queue has the write event state that indicates that the first instruction is to write the second register and is allocated into the first instruction queue, dispatching the first instruction to the at least one execution circuit.

17 . A system comprising:
a processor comprising:
one or more execution circuits to execute instructions;
a plurality of registers;
a first instruction queue to store memory instructions to be dispatched to the one or more execution circuits;
a second instruction queue to store arithmetic instructions to be dispatched to the one or more execution circuits;
a plurality of program order queues each associated with one of the plurality of registers, wherein a first program order queue associated with a first register comprises a plurality of entries each to store a state of an instruction that accesses the first register, and a second program order queue associated with a second register comprise

Assignees

• Intel Corp

Inventors

• Ayupov Andrey
• Srinivasan Srikanth T
• Pearce Jonathan D
• Sheffield David B

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3814

  Implementation provisions of instruction buffers, e.g. prefetch buffer; banks · CPC title

• G06F9/384

  Register renaming · CPC title