Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2020303393-A1
Application number	US-201916569215-A
Country	US
Kind code	A1
Filing date	Sep 12, 2019
Priority date	Mar 18, 2019
Publication date	Sep 24, 2020
Grant date	—

Abstract

A semiconductor memory device according to an embodiment includes a semiconductor substrate; a laminated body formed by laminating a plurality of electrode layers on the semiconductor substrate; a memory film provided in the laminated body and including a first block insulation film disposed in a direction perpendicular to the electrode layer, a charge storage film facing the first block insulation film, a tunnel insulation film facing the charge storage film, and a channel film facing the tunnel insulation film; and a barrier layer provided at at least one of interface between the plurality of electrode layers and the memory film and an interface in the memory film and mainly composed of carbon.

First claim

1 . A semiconductor memory device comprising:
a semiconductor substrate; a laminated body formed by laminating a plurality of electrode layers on the semiconductor substrate; a memory film provided in the laminated body and including a first block insulation film disposed in a direction perpendicular to the electrode layers, a charge storage film facing the first block insulation film, a tunnel insulation film facing the charge storage film, and a channel film facing the tunnel insulation film; and a barrier layer provided at at least one of an interface between the plurality of electrode layers and the memory film and an interface in the memory film and mainly composed of carbon.

2 . The semiconductor memory device according to claim 1 , wherein
each of the plurality of electrode layers includes a metal layer, a barrier metal layer covering the metal layer, and a second block insulation film covering the barrier metal layer, and the barrier layer is provided at an interface between the first block insulation film and the second block insulation film.

3 . The semiconductor memory device according to claim 1 , wherein the barrier layer is provided at an interface between the first block insulation film and the charge storage film.

4 . The semiconductor memory device according to claim 1 , wherein the barrier layer is provided at an interface between the charge storage film and the tunnel insulation film.

5 . The semiconductor memory device according to claim 1 , wherein
the tunnel insulation film includes a first film facing the charge storage film and a second film facing the channel film, and the oxygen concentration of the second film is greater than the oxygen concentration of the first film, and the barrier layer is provided at an interface between the first film and the second film.

6 . The semiconductor memory device according to claim 1 , wherein
the charge storage film includes a first silicon nitride layer facing the first block insulation film, a silicon oxynitride layer facing the first silicon nitride layer, and a second silicon nitride layer facing the silicon oxynitride layer, and the barrier layer contains the carbon, silicon, and nitrogen.

7 . The semiconductor memory device according to claim 1 , wherein
the charge storage film includes a first silicon nitride layer facing the first block insulation film, a silicon oxide layer facing the first silicon nitride layer, and a second silicon nitride layer facing the silicon oxide layer, and the barrier layer contains the carbon, silicon, and nitrogen.

8 . The semiconductor memory device according to claim 1 , wherein
the charge storage film includes a first silicon oxynitride layer facing the first block insulation film, a second silicon oxynitride layer facing the first silicon oxynitride layer, and a third silicon oxynitride layer facing the second silicon oxynitride layer, and the oxygen content of the second silicon oxynitride layer is greater than the oxygen content of each of the first silicon oxynitride layer and the third silicon oxynitride layer, and the barrier layer contains the carbon, silicon, and nitrogen.

9 . The semiconductor memory device according to claim 1 , wherein
the charge storage film includes a first silicon nitride layer facing the first block insulation film, a first silicon oxynitride layer facing the first silicon nitride layer, a second silicon nitride layer facing the first silicon oxynitride layer, a second silicon oxynitride layer facing the second silicon nitride layer, and a third silicon nitride layer facing the second silicon oxynitride layer, and the barrier layer contains the carbon, silicon, and nitrogen.

10 . The semiconductor memory device according to claim 1 , wherein
the charge storage film includes a first silicon nitride layer facing the first block insulation film, a first silicon oxide layer facing the first silicon nitride layer, a second silicon nitride layer facing the first silicon oxide layer, a second silicon oxide layer facing the second silicon nitride layer, and a third silicon nitride layer facing the second silicon oxide layer, and the barrier layer contains the carbon, silicon, and nitrogen.

11 . The semiconductor memory device according to claim 1 , wherein
the charge storage film includes a first silicon oxynitride layer facing the first block insulation film, a second silicon oxynitride layer facing the first silicon oxynitride layer, a third silicon oxynitride layer facing the second silicon oxynitride layer, a fourth silicon oxynitride layer facing the third silicon oxynitride layer, and a fifth silicon oxynitride layer facing the fourth silicon oxynitride layer, the oxygen content of the second silicon oxynitride layer is greater than the oxygen content of each of the first silicon oxynitride layer and the third silicon oxynitride layer, and the oxygen content of the fourth silicon oxynitride layer is greater than the oxygen content of each of the third silicon oxynitride layer and the fifth silicon oxynitride layer, and the barrier layer contains the carbon, silicon, and nitrogen.

12 . The semiconductor memory device according to claim 6 , wherein the silicon content of the first silicon nitride layer is less than the silicon content of the second silicon nitride layer.

13 . The semiconductor memory device according to claim 6 , wherein the silicon content of the first silicon nitride layer is greater than the silicon content of the second silicon nitride layer.

14 . The semiconductor memory device according to claim 9 , wherein the silicon content of the first silicon nitride layer is greater than the silicon content of the third silicon nitride layer.

15 . The semiconductor memory device according to claim 9 , wherein the silicon content of the first silicon nitride layer is less than the silicon content of the third silicon nitride layer.

16 . The semiconductor memory device according to claim 6 , wherein the barrier layer is provided at an interface between the first silicon nitride layer and the silicon oxynitride layer.

17 . The semiconductor memory device according to claim 7 , wherein the barrier layer is provided at an interface between the first silicon nitride layer and the silicon oxide layer.

18 . The semiconductor memory device according to claim 8 , wherein the barrier layer is provided at an interface between the first silicon oxynitride layer and the second silicon oxynitride layer.

19 . The semiconductor memory device according to claim 9 , wherein the barrier layer is provided at at least one of interface between the first silicon nitride layer and the first silicon oxynitride layer and an interface between the second silicon nitride layer and the second silicon oxynitride layer.

20 . The semiconductor memory device according to claim 10 , wherein the barrier layer is provided at at least one of interface between the first silicon nitride layer and the first silicon oxide layer and an interface between the second silicon nitride layer and the second silicon oxide layer.

Assignees

• Toshiba Memory Corp

Inventors

• Fujitsuka Ryota
• Yamada Kenta
• Yamanaka Takanori
• Okada Takayuki
• Ishigaki Hirokazu
• Kishi Hiroki
• Matsuura Nobushi
• Yamane Takashi
• Suzuki Ryota

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6682

  the compound being a silane, e.g. disilane, methylsilane or chlorosilane · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10D64/514

  characterised by the insulating layers · CPC title

• H10D64/037 Primary

  comprising charge-trapping insulators · CPC title