Ceramic substrate

Patent metadata

Field	Value
Publication number	US-2020296828-A1
Application number	US-202016745114-A
Country	US
Kind code	A1
Filing date	Jan 16, 2020
Priority date	Mar 11, 2019
Publication date	Sep 17, 2020
Grant date	—

Abstract

A ceramic substrate capable of suppressing the reduced reliability caused by via misalignment during manufacturing, and capable of suppressing the reduced reliability caused by thermal stress between the ceramic substrate and a mounting board is provided. The ceramic substrate includes an electrode and a via connected to the electrode. The ceramic substrate includes a plurality of vias provided to a center portion in a first direction of the electrode along a second direction. The first direction is parallel to a surface on which the electrode is disposed. The first direction is a direction connecting a center of the surface to a center of the electrode. The second direction is parallel to the surface and perpendicular to the first direction.

First claim

What is claimed is:

1 . A ceramic substrate comprising:
an electrode; and a via connected to the electrode, wherein a plurality of the vias are provided to a center portion in a first direction of the electrode along a second direction, the first direction is parallel to a surface on which the electrode is disposed, the first direction is a direction connecting a center of the surface to a center of the electrode, and the second direction is parallel to the surface and perpendicular to the first direction.

2 . The ceramic substrate according to claim 1 ,
wherein the ceramic substrate includes a plurality of the electrodes on the surface, and wherein the plurality of vias are provided to the center portion in the first direction of each of the electrodes along the second direction of each of the electrodes.

3 . The ceramic substrate according to claim 1 ,
wherein the ceramic substrate includes a plurality of the electrodes disposed at predetermined intervals in each of a third direction and a fourth direction, and the third direction and the fourth direction are parallel to the surface and mutually orthogonal, and wherein on at least an outer circumference along an outer edge of the surface, the plurality of vias are provided to the center portion in the first direction of each of the electrodes along the second direction of each of the electrodes.

4 . The ceramic substrate according to claim 3 ,
wherein the plurality of electrodes are disposed on intersection points of a plurality of straight lines parallel to the third direction and a plurality of straight lines parallel to the fourth direction.

5 . The ceramic substrate according to claim 1 ,
wherein the ceramic substrate has a multilayer structure in which a plurality of ceramic layers are laminated, wherein a plurality of inner layer vias are provided to the ceramic layer inside the ceramic layer on the surface side on which the via is provided, and wherein the plurality of inner layer vias are provided in the second direction at intervals different from intervals of the vias on the surface side, and at least partially connected to the vias on the surface side.

6 . The ceramic substrate according to claim 5 , further comprising
a plurality of primary side electrodes on a surface on an opposite side of the surface, the plurality of primary side electrodes being connected to a semiconductor element, wherein a plurality of the electrodes are disposed in a wide range compared with the plurality of primary side electrodes, and the plurality of electrodes are secondary side electrodes connected to a mounting board, and wherein the primary side electrodes are connected to the respective secondary side electrodes via at least a part of the plurality of vias and at least a part of the plurality of inner layer vias.

7 . The ceramic substrate according to claim 1 , further comprising
a resist layer that covers the surface including a peripheral edge portion of the electrode, wherein a part of the plurality of vias is connected to the peripheral edge portion.

Assignees

• Hitachi Metals Ltd

Inventors

• Tanie Hisashi
• Hayashi Kenji
• Shimazu Hiromi

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/692

  Ceramics or glasses · CPC title