Systems and methods for powering an integrated circuit having multiple interconnected die

US2020286858A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2020286858-A1
Application numberUS-202016810520-A
CountryUS
Kind codeA1
Filing dateMar 5, 2020
Priority dateMar 5, 2019
Publication dateSep 10, 2020
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

The power on wafer assembly can include: a compliant connector, an integrated circuit, a printed circuit board (PCB), a power component, and a set of compliant connectors. The power on wafer assembly can optionally include: a compression element, a cooling system, a set of mechanical clamping components, and a power source. However, the power on wafer assembly can additionally or alternately include any other suitable components.

First claim

Opening claim text (preview).

1 . An assembly comprising: a printed circuit board (PCB) defining a first surface of the PCB; a semiconductor, defining a second surface of the semiconductor, comprising: a substrate; and a first die and a second die formed within the substrate; a first and second power converter arranged between the first surface of the PCB and the second surface of the semiconductor, the first and second power converters electrically connected to the first and second die, respectively; and a compliant connector electrically connecting the PCB and the first power converter; wherein the second power converter is electrically coupled to the PCB. 2 . The assembly of claim 1 , wherein the semiconductor further comprises: a circuit layer formed at each of the first and second die; and a plurality of inter-die connections communicatively connecting the first and second die. 3 . The assembly of claim 1 , further comprising a compression element arranged between the PCB and the first power converter. 4 . The assembly of claim 3 , wherein the compression element comprises the compliant connector. 5 . The assembly of claim 3 , further comprising a plurality of clamping components mechanically coupling the PCB to the semiconductor and preloading the compression element. 6 . The assembly of claim 1 , further comprising a first cold plate, arranged between the first power converter and the PCB, that is thermally connected to the first power converter. 7 . The assembly of claim 6 , further comprising: a fluid reservoir; and a fluid manifold extending through a thickness of the PCB and connecting the first cold plate to the reservoir. 8 . The assembly of claim 6 , further comprising: a second cold plate arranged proximate a second surface of the integrated circuit opposite the second surface of the semiconductor; and a fluid manifold fluidly connecting the first cold plate and the second cold plate. 9 . The assembly of claim 1 , wherein the semiconductor comprises a wafer-scale processor. 10 . The assembly of claim 1 , wherein the power converter comprises a voltage regulator, a current transformer, and a driver. 11 . The assembly of claim 1 , further comprising: a power source opposing the first power converter across a thickness of the PCB; and a through silicon via (TSV) extending through a thickness of the PCB, the TSV electrically connecting the power source to the compliant connector. 12 . An assembly comprising: a printed circuit board (PCB) defining a first surface of the PCB; an integrated circuit having a set of conductive pads arranged along a second surface of the integrated circuit; a power converter arranged between first surface of the PCB and the second surface of the integrated circuit, the power converter electrically connected to each of the set of conductive pads; and a compliant connector extending between the PCB and the power converter. 13 . The assembly of claim 12 , further comprising a compression element, comprising the complaint connector, arranged between the PCB and the first power converter. 14 . The assembly of claim 12 , wherein the integrated circuit comprises a wafer-scale processor. 15 . The assembly of claim 12 , further comprising a first cold plate arranged between the power converter and the PCB, the first cold plate thermally connected to the power converter. 16 . The assembly of claim 15 , wherein the first cold plate is mechanically biased away from the PCB. 17 . The assembly of claim 15 , wherein: the first cold plate is thermally connected to the power converter at a first region on a broad face of the power converter, and the compliant connector is electrically connected to the power converter at a second region on the broad face of the power converter, the second region separate and distinct from the first region. 18 . The assembly of claim 17 , wherein the second region comprises a periphery of the broad face of the first power component. 19 . The assembly of claim 12 , wherein the power converter comprises a voltage regulator. 20 . The assembly of claim 12 , wherein the integrated circuit further comprises: a substrate; a plurality of die formed with the substrate; a circuit layer formed at each of the plurality of die; a plurality of inter-die connections that communicatively connect disparate die formed with the substrate, wherein each of the plurality of inter-die connections extends between each pair of adjacent die of the plurality of die, wherein each of the plurality of inter-die connections comprises a conductive material that is the same as the conductive material forming intra-die connections on the circuit layer of each die; a plurality of peripheral connections distinct from the plurality of inter-die connections are formed along at least one side of a subset of the plurality of die positioned along an outer periphery of the substrate; and a plurality of power converters comprising the power converter, wherein each of the plurality of die is connected to one or more of the plurality of power converters.

Assignees

Inventors

Classifications

  • between laterally-adjacent chips · CPC title

  • characterised by the relative positions of pads or connectors relative to package parts · CPC title

  • Detachable holders for supporting packaged chips in operation · CPC title

  • H10W70/635Primary

    Through-vias · CPC title

  • by flowing liquids, e.g. forced water cooling · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2020286858A1 cover?
The power on wafer assembly can include: a compliant connector, an integrated circuit, a printed circuit board (PCB), a power component, and a set of compliant connectors. The power on wafer assembly can optionally include: a compression element, a cooling system, a set of mechanical clamping components, and a power source. However, the power on wafer assembly can additionally or alternately in…
Who is the assignee on this patent?
Cerebras Systems Inc
What technology area does this patent fall under?
Primary CPC classification H10W70/635. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Sep 10 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).