Method and apparatus to control temperature of a semiconductor die in a computer system

Patent metadata

Field	Value
Publication number	US-2020286804-A1
Application number	US-201916292218-A
Country	US
Kind code	A1
Filing date	Mar 4, 2019
Priority date	Mar 4, 2019
Publication date	Sep 10, 2020
Grant date	—

Abstract

Circuitry to apply heat to a die while the die junction temperature is below a minimum die junction temperature of an operating die junction temperature range for the die is provided. The circuitry to avoid a system boot failure when the die junction temperature is below the operating die junction temperature range of the die.

First claim

1 . An apparatus comprising:
a die to operate in an overclocked mode; and circuitry to apply supplemental heat to the die while a die junction temperature is below an operating temperature range for the die junction temperature.

2 . The apparatus of claim 1 , wherein the supplemental heat is applied if the die junction temperature is below the operating temperature range for the die junction temperature after liquid nitrogen or liquid helium is applied to the die.

3 . The apparatus of claim 2 , wherein the supplemental heat is removed when the die junction temperature is within the operating temperature range for the die.

4 . The apparatus of claim 1 , wherein the circuitry is included in the die and the die is a System on Chip.

5 . The apparatus of claim 1 , wherein the circuitry includes a microcontroller communicatively coupled to the die.

6 . The apparatus of claim 1 , wherein the die is a central processing unit die and the circuitry is in a chipset die.

7 . The apparatus of claim 1 , wherein the circuitry is in a complex programmable logic device (CPLD).

8 . A method comprising:
applying power to a die; and applying supplemental heat to the die while a die junction temperature is below an operating temperature range for the die junction temperature.

9 . The method of claim 8 , wherein the supplemental heat is applied prior to start of a boot process if the die junction temperature is below the operating temperature range for the die junction temperature.

10 . The method of claim 9 , wherein the supplemental heat is removed when the die junction temperature is within the operating temperature range for the die.

11 . The method of claim 8 , wherein the supplemental heat is applied by the circuitry included in the die and the die is a System on Chip.

12 . The method of claim 8 , wherein the circuitry includes a microcontroller communicatively coupled to the die.

13 . The method of claim 8 , wherein the die is a central processing unit die and the supplemental heat is applied by the circuitry in a chipset die.

14 . The method of claim 8 , wherein the supplemental heat is applied by the circuitry in a complex programmable logic device (CPLD).

15 . A system comprising:
a processor; a display communicatively coupled to the processor; and circuitry to apply supplemental heat to the processor while a die junction temperature in the processor is below an operating temperature range for the die junction temperature.

16 . The system of claim 15 , wherein the supplemental heat is applied prior to start of a boot process if the die junction temperature is below the operating temperature range for the die junction temperature.

17 . The system of claim 16 , wherein the supplemental heat is removed when the die junction temperature is within the operating temperature range for the processor.

18 . The system of claim 15 , wherein the circuitry and the processor are in a System on Chip.

19 . The system of claim 15 , wherein the circuitry includes a microcontroller communicatively coupled to the die.

20 . The system of claim 15 , wherein the circuitry is in a chipset die.

Assignees

• Intel Corp

Inventors

• Fallin John
• Ragland Daniel J
• Douglas Jonathan P

Classifications

• H10W40/47

  by flowing liquids, e.g. forced water cooling · CPC title

• H10W40/10 Primary

  Arrangements for heating · CPC title

• H10W40/00 Primary

  Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60) · CPC title

• G06F11/3024

  where the computing system component is a central processing unit [CPU] · CPC title

• G06F11/0721

  within a central processing unit [CPU] · CPC title