Enhanced burst mode operation of a memory device

Patent metadata

Field	Value
Publication number	US-2020286556-A1
Application number	US-201916295969-A
Country	US
Kind code	A1
Filing date	Mar 7, 2019
Priority date	Mar 7, 2019
Publication date	Sep 10, 2020
Grant date	—

Abstract

A controller for a phase change memory forms a dedicated burst write partition in the phase change memory and initializes memory cells of the dedicated burst write partition to a SET state. Programming of selected memory cells in the dedicated burst write partition is carried out using only RESET pulses.

First claim

1 . A memory device comprising a memory controller configured to:
prepare a dedicated burst write partition within a non-volatile memory; execute a background operation to condition memory cells of the dedicated burst write partition by setting the memory cells to a SET state; and apply only state change pulses for a RESET state to program the dedicated burst write partition with data of a burst write operation.

2 . The memory device of claim 1 , wherein the non-volatile memory is a phase change memory.

3 . (canceled)

4 . The memory device of claim 1 , the controller further configured to identify a subset of memory cells of the dedicated burst write partition based on the data of the burst write operation.

5 . The memory device of claim 4 , the controller further configured to execute a foreground operation to program the dedicated burst write partition with the data of the burst write operation.

6 . (canceled)

7 . The memory device of claim 1 , the controller to set a size of the dedicated burst write partition based on burst write operation activity to the memory device.

8 . A memory device comprising:
a non-volatile memory; and a controller configured to:
prepare a dedicated burst write partition in the non-volatile memory;
initialize all operational memory cells of the dedicated burst write partition to a SET state during a background operation; and
direct burst write operations to the dedicated burst write partition using only RESET pulses.

9 - 10 . (canceled)

11 . The memory device of claim 8 , the controller configured to apply the RESET pulses to a selected subset of memory cells of the dedicated burst write partition.

12 . The memory device of claim 8 , the controller configured to execute a foreground operation to direct the burst write operations to the dedicated burst write partition.

13 . The memory device of claim 8 , the controller configured to set a size of the dedicated burst write partition based on expected burst write operation activity for the memory device and a latency of the background operation.

14 . A method comprising:
preparing a dedicated burst write partition in a phase change memory with a background operation of a memory device controller using only SET pulses; and programming a burst write operation to the dedicated burst write partition using only RESET pulses.

15 . The method of claim 14 , wherein the RESET pulses are applied to an identified subset of memory cells of the dedicated burst write partition.

16 . (canceled)

17 . The method of claim 14 , further comprising:
analyzing the burst write operation to identify a subset of memory cells of the dedicated burst write partition to which to apply the RESET pulses.

18 . The method of claim 14 , further comprising:
setting a size of the dedicated burst write partition based on burst write operation activity of a memory device.

19 . The method of claim 14 , further comprising:
setting a size of the dedicated burst write partition based on a latency requirement for the background operation.

20 . The method of claim 14 , further comprising:
setting a size of the dedicated burst write partition based on a burst write latency requirement for a memory device.

Assignees

• Western Digital Tech Inc

Inventors

• Bazarsky Alex
• Alrod Idan
• Sharon Eran
• Navon Ariel
• Petti Chris

Classifications

• G11C13/0004 Primary

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title

• G06F3/0644

  Management of space entities, e.g. partitions, extents, pools · CPC title