Insulated-gate semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2020273971-A1
Application number	US-201916726289-A
Country	US
Kind code	A1
Filing date	Dec 24, 2019
Priority date	Feb 25, 2019
Publication date	Aug 27, 2020
Grant date	—

Abstract

A method of manufacturing an insulated-gate semiconductor device, includes: digging a gate trench and a dummy trench; burying a dummy electrode in the dummy trench via a gate insulating film and burying a gate electrode in the gate trench via the gate insulating film; exposing an upper portion of the dummy electrode and selectively forming an insulating film for testing so as to cover the gate electrode; depositing a conductive film for testing on the dummy electrode and the insulating film for testing; and selectively testing an insulating property of the gate insulating film in the dummy trench by applying a voltage between the conductive film for testing and the charge transport, region.

First claim

What is claimed is:

1 . An insulated-gate semiconductor device comprising:
a charge transport region of a first conductivity-type; an injection control region of a second conductivity-type provided on the charge transport region; a main charge supply region of the first conductivity-type provide on the injection control region; a dummy electrode buried, via a gate insulating film, in a dummy trench penetrating the main charge supply region and the injection control region to reach the charge transport region; a gate electrode buried, via the gate insulating film, in a. gate trench penetrating the main charge supply region and the injection control region to reach the charge transport region; a first interlayer insulating film provided on the gate electrode; and a second interlayer insulating film provided on the dummy electrode, wherein the first interlayer insulating film having a stacked structure including a greater number of insulating films by at least one layer than the second interlayer insulating film.

2 . The insulated-gate semiconductor device of claim 1 , wherein:
the first interlayer insulating film includes the stacked structure implementing an insulating film for testing provided on the gate electrode, an insulating film for connection provided on the insulating film for testing, and an upper-layer insulating film provided on the insulating film for connection; and the second interlayer insulating film includes a stacked structure implementing the insulating film for connection and the upper-layer insulating film provided on the dummy electrode.

3 . The insulated-gate semiconductor device of claim 2 , wherein the insulating film for testing and the insulating film for connection are made of an identical material.

4 . A method of manufacturing an insulated-gate semiconductor device, comprising:
forming an injection control region of a second conductivity-type on a charge transport region of a first conductivity-type; forming a main charge supply region of the first conductivity-type on the injection control region; digging a gate trench and a dummy trench so as to penetrate the main charge supply region and the injection control region; burying a dummy electrode in the dummy trench via a gate insulating film and burying a gate electrode in the gate trench via the gate insulating film; selectively forming an insulating film for testing so as to expose an upper portion of the dummy electrode and cover the gate electrode; depositing a conductive film for testing on the dummy electrode and the insulating film for testing; and selectively testing an insulating property of the gate insulating film in the dummy trench by applying a voltage between the conductive film for testing and the charge transport region.

5 . The method of claim. 4 , further comprising removing the conductive film for testing after testing the insulating property.

6 . The method of claim 5 , further comprising:
depositing an insulating film for connection so as to cover the insulating film for testing after removing the conductive film for testing; opening a contact hole in the insulating film for connection; and forming a main charge supply electrode electrically connected to the main charge supply region via the contact hole.

7 . The method of claim 5 . further comprising:
depositing an insulating film for connection so as to cover the insulating film for testing after removing the conductive film for testing; depositing an upper-layer insulating film so as to cover the insulating film for connection opening a contact hole in each of the insulating film for connection and the upper-layer insulating film; and forming a main charge supply electrode electrically connected to the main charge supply region via the contact holes.

Assignees

• Fuji Electric Co Ltd

Inventors

• Ishikawa Takamasa
• Noguchi Seiji

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title