Camera system with multiple camera

Patent metadata

Field	Value
Publication number	US-2020267302-A1
Application number	US-201916280061-A
Country	US
Kind code	A1
Filing date	Feb 20, 2019
Priority date	Feb 20, 2019
Publication date	Aug 20, 2020
Grant date	—

Abstract

A camera system is provided and includes a processor, a first camera, a second camera, and a data bus. The processor transmits a first trigger signal to the first camera to enable the first camera outputting first data to the processor through the data bus. The first camera transmits a second trigger signal to the second camera to enable the second camera outputting second data to the processor through the data bus.

First claim

1 . A camera system, comprising:
a processor having a data receiving terminal and a camera trigger terminal; a first camera having a trigger input terminal, a trigger output terminal, and a data output terminal, wherein the trigger input terminal is electrically connected to the camera trigger terminal of the processor; a second camera having a trigger input terminal and a data output terminal, wherein the trigger input terminal of the second camera is electrically connected to the trigger output terminal of the first camera; and a data bus electrically connected to the data receiving terminal of the processor, the data output terminal of the first camera, and the data output terminal of the second camera, wherein the processor transmits a first trigger signal to the first camera through the camera trigger terminal to enable the first camera outputting first data to the processor through the data bus, wherein the first camera transmits a second trigger signal to the second camera through the trigger output terminal of the first camera to enable the second camera outputting second data to the processor through the data bus, wherein the first camera starts to sense a first image after receiving the first trigger signal, and the first data comprises the first image, wherein the first camera transmits the second trigger signal to the second camera during a first period of the first camera outputting the first data to the processor through the data bus, wherein the data output terminal of the first camera is set to be in a high impedance state after the first camera outputs the first data to the processor.

2 . (canceled)

3 . The camera system of claim 1 , wherein the first camera enters a sleeping mode or a shutdown mode after outputting the first data to the processor.

4 . (canceled)

5 . The camera system of claim 1 , wherein the second camera starts to sense a second image after receiving the second trigger signal, wherein the second data comprises the second image,
wherein a period of the second camera sensing the second image at least partially overlaps with the first period of the first camera outputting the first data.

6 . The camera system of claim 5 , wherein the second camera enters a sleeping mode or a shutdown mode after outputting the second data to the processor.

7 . The camera system of claim 5 , wherein the first period of the first camera outputting the first data is directly followed by a second period of the second camera outputting the second data, and the first period does not overlap with the second period.

8 . The camera system of claim 1 ,
wherein the first camera transmits the second trigger signal to the second camera during a period of the first camera sensing the first image.

9 . The camera system of claim 8 , wherein the second camera starts to sense a second image after receiving the second trigger signal, and the second data comprises one or a plurality of rows of pixels of the second image,
wherein a period of the second camera sensing the second image at least partially overlaps with the period of the first camera sensing the first image, wherein a second period of the first camera outputting the first data is directly followed by a third period of the second camera outputting the second data, and the second period does not overlap with the third period.

10 . The camera system of claim 1 , wherein the processor further comprising:
a data sync terminal electrically connected to a sync terminal of the first camera and a sync terminal of the second camera; a data clock terminal electrically connected to a data clock terminal of the first camera and a data clock terminal of the second camera; a data control interface electrically connected to a control interface of the first camera and a control interface of the second camera; and a clock output terminal electrically connected to a clock input terminal of the first camera and a clock input terminal of the second camera.

Assignees

• Himax Imaging Ltd

Inventors

• Mittra Amit
• Chiang Tony

Classifications

• H04N23/90

  Arrangement of cameras or camera modules, e.g. multiple cameras in TV studios or sports stadiums · CPC title

• H04N23/661 Primary

  Transmitting camera control signals through networks, e.g. control via the Internet · CPC title

• H04N23/651

  for reducing power consumption by affecting camera operations, e.g. sleep mode, hibernation mode or power off of selective parts of the camera · CPC title

• H04N23/60

  Control of cameras or camera modules · CPC title

• H04N7/181 Primary

  for receiving images from a plurality of remote sources · CPC title