Power detector with all transistors being bipolar junction transistors

Patent metadata

Field	Value
Publication number	US-2020266764-A1
Application number	US-201916584897-A
Country	US
Kind code	A1
Filing date	Sep 26, 2019
Priority date	Feb 19, 2019
Publication date	Aug 20, 2020
Grant date	—

Abstract

A power detector has a signal input terminal, N limiting amplifiers, N rectifiers and a signal output terminal. N is an integer greater than 1. The signal input terminal receives an input signal, and the signal output terminal outputs a detection signal. The N limiting amplifiers generate N amplified signals according to N attenuated signals having different attenuation. Each limiting amplifier receives one of the N attenuated signals and outputs one of the N amplified signals. Each rectifier receives a corresponding amplified signal and outputs a rectified signal. The detection signal is associated with the sum of N rectified signals outputted from the N rectifiers, and all transistors of the power detector are bipolar junction transistors.

First claim

What is claimed is:

1 . A power detector, comprising:
a signal input end for receiving an input signal; N limiting amplifiers for generating N amplified signals according to N attenuated signals having different attenuation amounts, N being an integer greater than 1 , wherein the N attenuated signals are related to the input signal, and each of the N limiting amplifiers comprises:
a first input end for receiving one of the N attenuated signals; and
a first output end for outputting one of the N amplified signals;
N rectifiers coupled to the N limiting amplifiers, each of the N rectifiers comprising:
a first input end for receiving an amplified signal output by a first output end of a corresponding N limiting amplifier; and
an output end for outputting a rectified signal; and
a signal output end for outputting a detection signal; wherein the detection signal is related to a sum of N rectified signals output by the N rectifiers, and all transistors of the power detector are bipolar junction transistors (BJTs).

2 . The power detector of claim 1 , wherein the detection signal is a voltage signal, and the power detector further comprises a conversion circuit for converting the sum of the N rectified signals output by the N rectifiers into the voltage signal.

3 . The power detector of claim 2 , wherein the conversion circuit comprises a conversion resistor, a first end of the conversion resistor is coupled to a system voltage, and a second end of the conversion resistor is coupled to the signal output end.

4 . The power detector of claim 1 , further comprising an attenuation circuit, the attenuation circuit comprising:
an input end coupled to the signal input end; and N output ends for respectively outputting the N attenuated signals to first input ends of the N limiting amplifiers.

5 . The power detector of claim 4 , further comprising:
an inverting amplifier coupled to the N rectifiers for performing amplification and inversion processes according to the sum of the N rectified signals output by the N rectifiers so as to output the detection signal, the inverting amplifier comprising:
an input end coupled to output ends of the N rectifiers; and
an output end coupled to the signal output end of the power detector for outputting the detection signal;
an N+1 th limiting amplifier, coupled to the signal input end, and comprising:
a first input end for receiving an N+1 th attenuated signal; and
a first output end for outputting an N+1 th amplified signal; and
an N+l th rectifier coupled to the N+1 th limiting amplifier, and comprising:
a first input end for receiving the N+1 th amplified signal; and
an output end for outputting an N+1 th rectified signal;
wherein the inverting amplifier is further coupled to the N+1 th rectifier for performing amplification and inversion processes according to a sum of the N+1 rectified signals output by the N+1 rectifiers so as to output the detection signal.

6 . The power detector of claim 5 , wherein each limiting amplifier further comprises:
a first transistor having a control end coupled to the first input end of the each limiting amplifier; a second transistor having a control end coupled to a second input end of the each limiting amplifier; a first resistor having a first end coupled to a system voltage and a second end coupled to the first output end of the each limiting amplifier; a second resistor having a first end coupled the system voltage and a second end coupled to the second output end of the each limiting amplifier; a third transistor having a first end coupled to the first output end of the each limiting amplifier, a second end coupled to a first end of the first transistor, and a control end coupled to a first limiting amplifier bias; a fourth transistor having a first end coupled to the second output end of the each limiting amplifier, a second end coupled to a first end of the second transistor, and a control end coupled to the first limiting amplifier bias; and a fifth transistor having a first end coupled to a second end of the first transistor and a second end of the second transistor, a second end coupled to a reference voltage, and a control end coupled to a second limiting amplifier bias.

7 . The power detector of claim 6 , further comprising a limiting amplifier bias circuit, wherein the limiting amplifier bias circuit comprises:
a sixth transistor having a first end coupled to a current source and a second end coupled to the reference voltage; a seventh transistor having a first end coupled to the system voltage and a control end coupled to the current source; a first resistor having a first end coupled to the control end of the sixth transistor, and a second end coupled to the second end of the seventh transistor for outputting the second limiting amplifier bias; a first capacitor having a first end coupled to the second end of the first resistor and a second end coupled to the reference voltage; a second resistor having a first end coupled to the system voltage and a second end for outputting the first limiting amplifier bias; and a third resistor having a first end coupled to the second end of the second resistor.

8 . The power detector of claim 5 , wherein each rectifier further comprises:
a first transistor having a first end coupled to the output end of the each rectifier, and a control end coupled to the first output end of a corresponding limiting amplifier; a second transistor having a first end coupled to the output end of the each rectifier, and a control end coupled to a second output end of the corresponding limiting amplifier; a first resistor having:
a first end coupled to a second end of the first transistor and a second end of the second transistor; and
a second end coupled to a reference voltage;
a second resistor having:
a first end coupled to the control end of the first transistor; and
a second end coupled to a rectifying bias; and
a third resistor having:
a first end coupled to the control end of the second transistor; and
a second end coupled to the rectifying bias.

9 . The power detector of claim 8 further comprising a rectifier bias circuit, and the rectifier bias circuit comprising:
a third transistor having a first end coupled to a current source; and
a fourth transistor having a first end coupled to a system voltage and a control end coupled to the current source.

10 . The power detector of claim 9 , wherein the first transistor has the same width-to-length ratio (W/L ratio) as the fourth transistor.

11 . The power detector of claim 5 , wherein each of the N+ 1 rectifiers is a class-B full-wave rectifier.

12 . The power detector of claim 5 , wherein the attenuation circuit further comprises N attenuation units, wherein:
an input end of a first attenuation unit of the N attenuation units is coupled to the signal input end, and an output end of the first attenuation unit of the N attenuation units is coupled to the first output end of the N output ends; and an input end of an m th attenuation unit of the N attenuation units is coupled to an (m−1) th output end of the N output ends, an output end of the m th attenuation unit of the N attenuation units is coupled to an m th output end of the N output ends, and 1<m≤N.

13 . The power detector of claim 12 , wherein each attenuation unit comprises:
a first resistor having a first end coupled to an input end of the each attenuation unit and a second end coupled to an output end of the each attenuation unit; and a second resistor having a first end coupled to the output end of the each attenuation unit and a seco

Assignees

• Richwave Technology Corp

Inventors

• Chien Hwey-Ching

Classifications

• H03G7/001 Primary

  without controlling loop (H03G7/007, H03G7/02, H03G7/06 take precedence) · CPC title

• H03F1/02

  Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation · CPC title

• G06G7/24

  for evaluating logarithmic or exponential functions, e.g. hyperbolic functions {(for multiplication, division or for evaluating powers or roots using logarithmic functions; gamma correction in television systems H04N5/20, H04N9/69)} · CPC title

• G01R19/00

  Arrangements for measuring currents or voltages or for indicating presence or sign thereof (G01R5/00 takes precedence; for measuring bioelectric currents or voltages A61B5/24) · CPC title

• G01R21/01

  in circuits having distributed constants (G01R21/04, G01R21/07, G01R21/09, G01R21/12 take precedence) · CPC title