Systems and methods for balancing multiple partitions of non-volatile memory

Patent metadata

Field	Value
Publication number	US-2020264792-A1
Application number	US-201916277230-A
Country	US
Kind code	A1
Filing date	Feb 15, 2019
Priority date	Feb 15, 2019
Publication date	Aug 20, 2020
Grant date	—

Abstract

Systems and methods for balancing multiple partitions of non-volatile memory devices are provided. Embodiments discussed herein execute a balance proportion scheme in connection with a NVM that is partitioned to have multiple partition types. Each partition type has an associated endurance that defines an average number of program/erase (P/E) cycles it can endure before it reaches failure. For example, a first partition type may have a substantially greater endurance than a second partition type. The balance proportion scheme ensures that, even though each partition type has a different associated endurance, all partition types are used proportionally with respect to each other to balance their respective P/E cycles. This way, both partition types will reach the upper limits of their respective endurance levels out at approximately the same time.

First claim

What is claimed is:

1 . A system, comprising:
non-volatile memory comprising first partition and second partition each having a different program/erase endurance; and control circuitry configured to:
access parameters associated with each of the first partition and the second partition, wherein the parameters comprise program/erase cycles for each of the first partition and the second partition;
determine a difference between program/erase cycles of the first partition and program/erase cycles of the second partition;
adjust a balance proportion scheme based on the difference; and
execute write operations by directing data to the first partition and the second partition in accordance with the adjusted balance proportion scheme.

2 . The system of claim 1 , wherein the balance proportion scheme specifies a first partition proportion and a second partition proportion, and wherein the data is directed to the non-volatile memory based on the first partition proportion and the second partition proportion.

3 . The system of claim 1 , wherein the balance proportion scheme maintains balances writes to the first partition and the second partition such that the program/erase cycles of the first partition approximate a 1-to-1 scaled parity with the program/erase cycles of the second partition.

4 . The system of claim 1 , wherein the balance proportion scheme maintains balances writes to the first partition and the second partition such that the program/erase cycles of the first partition and the program/erase cycles of the second partition both approximate an ideal endurance slope.

5 . The system of claim 1 , wherein the control circuitry is further configured to:
adjust the balance proportion scheme by selecting a balance proportion schedule from a plurality of balance proportion schedules based on the difference; and execute write operations by directing data to the first partition and the second partitions in accordance with the selected balance proportion schedule.

6 . The system of claim 1 , wherein the control circuitry is further configured to:
re-determine the difference in response to a rebalance event; and adjust the balance proportion scheme based on the re-determined difference.

7 . A method implemented in a system comprising non-volatile memory comprising a first partition and a second partition each having different program/erase endurances, the method comprising:
accessing parameters associated with each of the first partition and the second partition; evaluating the parameters to determine whether the first partition or the second partition is overheating, wherein overheating indicates that one of the first partition and second partition has a higher proportional usage than the other partition; in response to determining that the first partition is overheating, implementing a first balancing scheme that balances a proportional usage of the first partition relative to the second partition to prevent the first partition from prematurely reaching an end of life parameter; in response to determining that the second partition is overheating, implementing a second balancing scheme that balances a proportional usage of the second partition relative to the first partition to prevent the second partition from prematurely reaching the end of life parameter; and executing write operations by directing data to the first and second partitions in accordance with the first balancing scheme or the second balancing scheme.

8 . The method of claim 7 , wherein the first partition is a single-level cell partition, and wherein the second partition is a multi-level cell partition.

9 . The method of claim 7 , wherein implementing the first balancing scheme comprises:
calculating a difference between first partition usage and second partition usage based on the received parameters; selecting one of a plurality of balance proportion schedules based on the calculated difference, wherein each of the balance proportion schedules specifies a first partition proportion and a second partition proportion; and directing write data to the first and second partitions in accordance with the first partition proportion and the second partition proportion.

10 . The method of claim 9 , wherein the difference is a difference percentage, and wherein each of the plurality of balance proportion schedules comprises a percentage range, a unit value for the first partition proportion, and a unit value for the second partition proportion.

11 . The method of claim 10 , wherein each unit of the unit values for the first and second partition portions corresponds to a portion of a band.

12 . The method of claim 7 , wherein implementing the first balancing scheme comprises:
determining an endurance slope of the first partition based on the parameters; assessing whether a difference between the endurance slope of the first partition and an ideal endurance slope exceeds a threshold; and in response to an assessment that the difference exceeds the threshold, adjusting the proportional usage of the first partition relative to the second partition to alter the endurance slope to more closely align with the ideal endurance slope.

13 . The method of claim 7 , wherein implementing the second balancing scheme comprises:
directing write data only to the first partition.

14 . A memory system, comprising:
non-volatile memory comprising a first partition and a second partition each having a different program/erase endurance; and control circuitry configured to direct write data to the first partition and the second partition according to a balance proportion scheme, wherein the balance proportion scheme balances data writes to the first and second partitions such that scaled program/erase cycles of the first partition is at or near parity with program/erase cycles of the second partition.

15 . The memory system of claim 14 wherein the scaled program/erase cycles is a scalar function based on a scalar difference between the different program/erase endurances of the first and second partitions.

16 . The memory system of 14 , wherein the first partition is a single-level cell partition, and wherein the second partition is a multi-level cell partition.

17 . The memory system of claim 14 , wherein the control circuitry is configured to:
direct a first number of units of write data to the first partition based on the balance proportion scheme; and direct a second number of units of write data to the second partition based on the balance proportion scheme, wherein the first and second numbers of units are selected to maintain parity between the scaled program/erase cycles of the first partition and program/erase cycles of the second partition.

18 . The memory system of claim 17 , wherein a unit of write data to the first partition is equal to a portion of a band of the first partition, and wherein a unit of write data to the second partition is equal to a portion of a band of the second partition.

19 . The memory system of claim 18 , wherein the portion of the band of the first partition is ⅛ th of the band, and wherein the portion of the band of the second partition is ⅛ th of the band.

20 . The memory system of claim 14 , wherein the non-volatile memory is a nand memory.

Assignees

• Apple Inc

Inventors

• Paley Alexander
• Vogan Andrew W

Classifications

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0644 Primary

  Management of space entities, e.g. partitions, extents, pools · CPC title

• G06F3/0616

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title

• G06F2206/1012

  Load balancing · CPC title