Threshold computation circuit for s-fsk receiver, integrated circuit, and method associated therewith

Patent metadata

Field	Value
Publication number	US-2020259690-A1
Application number	US-201916450065-A
Country	US
Kind code	A1
Filing date	Jun 24, 2019
Priority date	Feb 12, 2019
Publication date	Aug 13, 2020
Grant date	—

Abstract

A threshold computation circuit includes an input circuit, a maximum filter circuit, a minimum filter circuit, and a calculating circuit. The input circuit receives a discrete frequency signal from a digital filtering circuit. The discrete frequency signal is based on an S-FSK waveform received by an S-FSK receiver associated with the digital filtering circuit. The discrete frequency signal is representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. The maximum filter circuit adjusts a maximum amplitude parameter based on the discrete frequency signal and a predetermined threshold. The minimum filter circuit adjusts a minimum amplitude parameter based on the discrete frequency signal and the predetermined threshold. The calculating circuit adapts the predetermined threshold for a next data frame based on the maximum and minimum amplitude parameters. An integrated circuit and a method for computing the threshold are also disclosed.

First claim

1 . A threshold computation circuit for a spread frequency-shift keying (S-FSK) receiver, the threshold computation circuit comprising:
an input circuit, configured to receive a discrete frequency signal from a digital filtering circuit, the discrete frequency signal is based on an S-FSK waveform received by an S-FSK receiver associated with the digital filtering circuit, the discrete frequency signal is representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform, each data frame including an active portion and a zero energy portion, the active portion includes at least one data word and the zero energy portion includes at least one zero energy word, each data word and zero energy word include multiple bit periods; a maximum filter circuit, configured to dynamically and selectively adjust a maximum amplitude parameter during bit periods of the series of data frames, the adjusting is based on the discrete frequency signal and a predetermined threshold value; a minimum filter circuit, configured to dynamically and selectively adjust a minimum amplitude parameter during bit periods of the series of data frames, the adjusting is based on the discrete frequency signal and the predetermined threshold value; and a calculating circuit, configured to adapt the predetermined threshold value for a next data frame based on the maximum amplitude parameter and the minimum amplitude parameter after a current data frame.

2 . The threshold computation circuit of claim 1 , in which the maximum filter circuit is configured to:
i) determine if the discrete frequency signal is greater than the predetermined threshold value during each bit period of the series of data frames, ii) modify the maximum amplitude parameter during each bit period of the current data frame in which the discrete frequency signal is greater than the predetermined threshold value to form a next maximum amplitude parameter for the next data frame, iii) count each bit period of the current data frame, and iv) change the maximum amplitude parameter to be equivalent to the next maximum amplitude parameter after counting the bit periods of the current data frame.

3 . The threshold computation circuit of claim 2 , in which the maximum filter circuit is configured to modify the maximum amplitude parameter in accordance with the following equation:
max amp param ( i+ 1)=(discrete freq sig( i ))/ m+ (1−1 /m )max amp param( i )

where i is a current bit period, max amp param (i+1) is the next maximum amplitude parameter for a next bit period, discrete freq sig(i) is the discrete frequency signal for the current bit period, m is less than two times an expected number of bit periods per data frame with “ON” logic levels, and max amp param (i) is the maximum amplitude parameter for the current bit period.

4 . The threshold computation circuit of claim 2 , in which the maximum filter circuit is configured to change the maximum amplitude parameter in accordance with the following equation:
max amp param ( i+ 1)=max amp param
where i is a current bit period, max amp param (i+1) is the next maximum amplitude parameter for a next bit period, and max amp param is the maximum amplitude parameter to be used for the next data frame.

5 . The threshold computation circuit of claim 1 , in which the minimum filter circuit is configured to:
i) determine if the discrete frequency signal is less than the predetermined threshold value during each bit period of the series of data frames, ii) modify the minimum amplitude parameter during each bit period of the current data frame in which the discrete frequency signal is less than the predetermined threshold value to form a next minimum amplitude parameter for the next data frame, iii) count each bit period of the current data frame, and iv) change the minimum amplitude parameter to be equivalent to the next minimum amplitude parameter after counting the bit periods of the current data frame.

6 . The threshold computation circuit of claim 5 , in which the minimum filter circuit is configured to modify the minimum amplitude parameter in accordance with the following equation:
min amp param ( i+ 1)=(discrete freq sig( i ))/ m+ (1−1 /m )min amp param( i )

where i is a current bit period, min amp param (i+1) is the next minimum amplitude parameter for a next bit period, discrete freq sig(i) is the discrete frequency signal for the current bit period, m is less than two times an expected number of bit periods per data frame with “ON” logic levels, and min amp param (i) is the minimum amplitude parameter for the current bit period.

7 . The threshold computation circuit of claim 5 , in which the minimum filter circuit is configured to change the minimum amplitude parameter in accordance with the following equation:
min amp param ( i+ 1)=min amp param
where i is a current bit period, min amp param (i+1) is the next minimum amplitude parameter for a next bit period, and min amp param is the minimum amplitude parameter to be used for the next data frame.

8 . The threshold computation circuit of claim 1 , in which the calculating circuit is configured to:
i) calculate an updated threshold value for the predetermined threshold value based on the maximum and minimum amplitude parameters after the current data frame, and ii) modify the predetermined threshold value for the next data frame based on the updated threshold value.

9 . The threshold computation circuit of claim 8 , in which the calculating circuit is configured to calculate the updated threshold value in accordance with the following equation:
updated thresh val=(max amp param+min amp param)/2
where updated thresh val is the updated threshold value calculated after the current data frame, max amp param is the maximum amplitude parameter after the current data frame, and min amp param is the minimum amplitude parameter after the current data frame.

10 . The threshold computation circuit of claim 8 , in which the calculating circuit is configured to modify the predetermined threshold value in accordance with the following equation:
updated thresh val=predetermined thresh
where updated thresh val is the updated threshold value calculated after the current data frame and predetermined thresh is the predetermined threshold value to be used for the next data frame.

11 . The threshold computation circuit of claim 1 , including:
a second input circuit, configured to receive a second frequency signal from the digital filtering circuit, the second frequency signal is based on the S-FSK waveform received by the S-FSK receiver, the second frequency signal is representative of second digital logic levels in the series of data frames modulated using S-FSK to form the S-FSK waveform; a second maximum filter circuit, configured to dynamically and selectively adjust a second maximum amplitude parameter during bit periods of the series of data frames, the adjusting is based on the second frequency signal and a second predetermined threshold value; a second minimum filter circuit, configured to dynamically and selectively adjust a second minimum amplitude parameter during bit periods of the series of data frames, the adjusting is based on the second frequency signal and the second predetermined threshold value; and a second calculating circuit, configured to adapt the second predetermined threshold value for the next data frame based on the second maximum amplitude parameter and the second minimum amplitude parameter after the current data frame.

12 . An integrated circuit, comprising:
a threshold computation circuit, including:

Assignees

• Texas Instruments Inc

Inventors

• Klemmer Nikolaus
• Akour Amneh Mohammed
• Patki Abhijit Anant
• Pauletti Timothy Patrick

Classifications

• H04L27/148 Primary

  using filters, including PLL-type filters · CPC title

• H04L27/14 Primary

  Demodulator circuits; Receiver circuits · CPC title

• H04B1/69

  Spread spectrum techniques · CPC title