Semiconductor devices having a seal ring
US-2024413245-A1 · Dec 12, 2024 · US
Semiconductor device
US2020258877A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2020258877-A1 |
| Application number | US-202016858934-A |
| Country | US |
| Kind code | A1 |
| Filing date | Apr 27, 2020 |
| Priority date | Mar 17, 2000 |
| Publication date | Aug 13, 2020 |
| Grant date | — |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.
First claim
Opening claim text (preview).
What is claimed is: 1 . A semiconductor device comprising: a first wiring layer defining a first direction and first virtual linear lines extending in a direction that traverses the first direction; and a plurality of dummy wiring layers provided in an identical level as the first wiring layer, wherein the first direction and the first virtual linear lines define an angle of 2 to 40 degrees, and the plurality of dummy wiring layers are disposed on the first virtual linear lines.
Assignees
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Classifications
by smoothing the dielectric parts · CPC title
using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title
by filling conductive material into holes, grooves or trenches · CPC title
- H10W20/43Primary
Layouts of interconnections · CPC title
Vias, e.g. via plugs · CPC title
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Frequently asked questions
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- What does patent US2020258877A1 cover?
- A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth dire…
- Who is the assignee on this patent?
- Seiko Epson Corp
- What technology area does this patent fall under?
- Primary CPC classification H10W20/43. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Aug 13 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).