Mutliple dielectrics for gate-all-around transistors

Patent metadata

Field	Value
Publication number	US-2020258786-A1
Application number	US-201916270174-A
Country	US
Kind code	A1
Filing date	Feb 7, 2019
Priority date	Feb 7, 2019
Publication date	Aug 13, 2020
Grant date	—

Abstract

A method is presented for attaining different gate dielectric thicknesses across a plurality of field effect transistor (FET) devices. The method includes forming interfacial and high-k dielectric layers around alternate semiconductor layers of the plurality of FET devices, pinching off gaps between the alternate semiconductor layers by depositing a high work function capping layer over the plurality of FET devices, selectively removing the high work function capping layer from a first set of the plurality of FET devices, depositing a sacrificial capping layer, with the sacrificial capping layer leaving gaps between the alternate semiconductor layers of the first set of the plurality of FET devices, depositing an oxygen blocking layer, and annealing the plurality of FET devices to create different gate dielectric thicknesses for each of the plurality of FET devices.

First claim

1 . A method for attaining different gate dielectric thicknesses across a plurality of field effect transistor (FET) devices, the method comprising:
forming interfacial and high-k dielectric layers around alternate semiconductor layers of the plurality of FET devices; pinching off gaps between the alternate semiconductor layers by depositing a high work function capping layer over the plurality of FET devices; selectively removing the high work function capping layer from a first set of the plurality of FET devices; depositing a sacrificial capping layer, with the sacrificial capping layer leaving gaps between the alternate semiconductor layers of the first set of the plurality of FET devices; depositing an oxygen blocking layer; and annealing the plurality of FET devices to create different gate dielectric thicknesses for each of the plurality of FET devices.

2 . The method of claim 1 , wherein the alternate semiconductor layers of the plurality of FET devices are silicon (Si) layers.

3 . The method of claim 1 , wherein the high work function capping layer has a work function value greater than 4.5 eV.

4 . The method of claim 1 , wherein the oxygen blocking layer includes amorphous silicon (a-Si).

5 . The method of claim 1 , wherein the plurality of FET devices includes a first FET device and a second FET device.

6 . The method of claim 5 , wherein the gate dielectric thicknesses of the first and second FET devices are successively larger.

7 . The method of claim 1 , wherein each of the plurality of FET devices attains a different gate dielectric thickness based on a different oxygen amount provided during the annealing.

8 . The method of claim 1 , further comprising depositing a high work function metal layer over the plurality of FET devices having the different gate dielectric thicknesses.

9 . The method of claim 1 , wherein the high work function capping layer includes ruthenium.

10 . A method for constructing devices with different gate dielectric thicknesses, the method comprising:
forming a first nanosheet stack for a first device and a second nanosheet stack for a second device; removing sacrificial layers from the first and second nanosheet stacks; forming interfacial and high-k dielectric layers around alternate semiconductor layers of the first and second devices; pinching off gaps between the alternate semiconductor layers by depositing a high work function capping layer; selectively removing the high work function capping layer from the first device; depositing a sacrificial capping layer, with the sacrificial capping layer leaving gaps between the alternate semiconductor layers of the first device; depositing an oxygen blocking layer; and annealing the first and second devices to create different gate dielectric thicknesses for each of the first and second devices.

11 . The method of claim 10 , wherein the sacrificial layers of the first and second nanosheet stacks are silicon germanium (SiGe) layers.

12 . The method of claim 10 , wherein the high work function capping layer has a work function value greater than 4.5 eV.

13 . The method of claim 10 , wherein the high work function capping layer includes ruthenium.

14 . The method of claim 10 , wherein the oxygen blocking layer includes amorphous silicon (a-Si).

15 . The method of claim 10 , wherein the gate dielectric thicknesses of the first and second devices are successively larger.

16 . The method of claim 10 , wherein the first device and the second device attain different gate dielectric thickness based on a different oxygen amount provided during the anneal.

17 . The method of claim 10 , further comprising depositing a high work function metal layer over the first and second devices each having a different gate dielectric thickness.

18 . A semiconductor structure for attaining different gate dielectric thicknesses across a plurality of field effect transistor (FET) devices, the semiconductor structure comprising:
a logic device including alternate semiconductor layers surrounded by an interfacial layer having a first gate dielectric thickness; an input/output (I/O) device including alternate semiconductor layers surrounded by an interfacial layer having a second gate dielectric thickness;

19 . The semiconductor structure of claim 16 , wherein a work function metal layer is disposed over the logic device and the I/O device each having a different gate dielectric thickness.

20 . The semiconductor structure of claim 16 , wherein the alternate semiconductor layers of the logic device and the I/O device are silicon (Si) layers.

Assignees

• IBM

Inventors

• Ando Takashi
• Zhang Jingyun
• Reznicek Alexander
• Lee Choonghyun
• Hashemi Pouya

Classifications

• H10P50/267

  using plasmas · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P14/3454

  Amorphous · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title