Wrap-Around Contact on FinFET

Patent metadata

Field	Value
Publication number	US-2020258784-A1
Application number	US-202016865049-A
Country	US
Kind code	A1
Filing date	May 1, 2020
Priority date	Apr 21, 2014
Publication date	Aug 13, 2020
Grant date	—

Abstract

A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

First claim

What is claimed is:

1 . A structure comprising:
a fin structure extending from a substrate; an epitaxial region over the fin structure, the epitaxial region having an upper surface and an under surface; a silicide region at the upper surface of the epitaxial region; a metal nitride layer on the upper surface and the under surface of the epitaxial region, the metal nitride layer directly contacting the silicide region; and a metal-comprising contact electrically connected to the epitaxial region, the metal nitride layer separating the metal-comprising contact from the upper surface and the under surface of the epitaxial region.

2 . The structure of claim 1 , wherein the silicide region comprises titanium, silicon, and germanium.

3 . The structure of claim 1 , wherein the metal nitride layer comprises titanium nitride.

4 . The structure of claim 1 , wherein the metal nitride layer has a thickness in a range of 1 nm to 4 nm.

5 . The structure of claim 1 , wherein the silicide region has a thickness in a range of 2 nm to 8 nm.

6 . The structure of claim 1 further comprising an etch stop layer on the under-surface of the epitaxial region, wherein etch stop layer is between the under-surface of the epitaxial region and the metal nitride layer.

7 . The structure of claim 1 further comprising:
a second fin structure extending upwards from the substrate and adjacent the fin structure;
a second epitaxial region over the second fin structure; and
a void between the epitaxial region and the second epitaxial region.

8 . The structure of claim 1 further comprising:
a shallow trench isolation (STI) region on a sidewall of the fin structure, wherein the metal nitride layer extends along a top surface of the STI region; and
a metal-comprising layer between the top surface of the STI region and the metal nitride layer.

9 . The structure of claim 8 , wherein the metal-comprising layer comprises titanium.

10 . A semiconductor device comprising:
a semiconductor fin; a gate structure over and extending along sidewalls of the semiconductor fin; a source/drain structure adjacent the gate structure; a dielectric layer on an underside of the source/drain structure; a metal-semiconductor compound at a top portion of the source/drain structure, wherein the metal-semiconductor compound comprises a metal and a semiconductor; a metal nitride layer on the metal-semiconductor compound, the dielectric layer separating the metal nitride layer from an under side of the source/drain structure; and a metal layer electrically connected to the source/drain structure through the metal nitride layer.

11 . The semiconductor device of claim 10 , wherein the dielectric layer comprises silicon nitride.

12 . The semiconductor device of claim 10 , wherein the metal nitride layer directly contacts the metal-semiconductor compound.

13 . The semiconductor device of claim 10 , wherein metal nitride layer comprises titanium nitride.

14 . The semiconductor device of claim 10 , wherein a thickness of the metal nitride layer is in a range of 1 nm to 4 nm.

15 . The semiconductor device of claim 10 further comprising a void under the underside of the source/drain structure.

16 . A semiconductor device comprising:
a first fin extending from a substrate; a shallow trench isolation (STI) region on a sidewall of the first fin; a first epitaxial region over the first fin; an etch stop layer physically contacting an under surface of the first epitaxial region; a first metal-comprising layer along an upper surface of the STI region; a barrier layer over the first metal-comprising layer, the barrier layer extends along the upper surface of the STI region and along an upper surface of the first epitaxial region; and a metal contact over the barrier layer, the metal contact is electrically connected to the first epitaxial region through the barrier layer.

17 . The semiconductor device of claim 16 , further comprising a silicide region in an upper portion of the first epitaxial region, wherein the barrier layer contacts the silicide region.

18 . The semiconductor device of claim 16 , the barrier layer comprises titanium nitride.

19 . The semiconductor device of claim 16 , wherein the first metal-comprising layer comprises titanium.

20 . The semiconductor device of claim 16 , wherein the barrier layer further extends along the under surface of the first epitaxial region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Sung-Li
• Chen Neng-Kuo
• Shih Ding-Kang
• Chang Meng-Chun
• Lin Yi-An
• Huang Gin-Chen
• Hsu Chen-Feng
• Lin Hau-Yu
• Ko Chih-Hsin
• Sun Sey-Ping
• Wann Clement Hsingjen

Classifications

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0147

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title