Shift register unit circuit and driving method, shift register, gate drive circuit, and display apparatus

Patent metadata

Field	Value
Publication number	US-2020258554-A1
Application number	US-201715766937-A
Country	US
Kind code	A1
Filing date	Oct 9, 2017
Priority date	Oct 27, 2016
Publication date	Aug 13, 2020
Grant date	—

Abstract

A shift register unit circuit includes an input sub-circuit, a pull-up sub-circuit, a pull-down control sub-circuit, a pull-down sub-circuit, and a voltage regulating sub-circuit. The input sub-circuit receives an input signal from a signal input terminal to control a potential of a pull-up node. The pull-up sub-circuit outputs a gate driving signal to an output terminal under control of the potential of the pull-up node and a signal from a first signal terminal. The pull-down control sub-circuit conducts a pull-down node with a first node under control of a signal from the second signal terminal. The pull-down sub-circuit conducts the pull-up node with the first node and the turn-down signal terminal with the output terminal under control of a potential of the pull-down node. The voltage regulating sub-circuit conducts the first node with the turn-down signal terminal under control of a potential of the first node.

First claim

1 . A shift register unit circuit, comprising:
an input sub-circuit coupled to a signal input terminal and a pull-up node, configured to receive an input signal from the signal input terminal to thereby control a potential of the pull-up node; a pull-up sub-circuit coupled to the pull-up node, a first signal terminal and an output terminal, configured to output a gate driving signal to the output terminal under control of the potential of the pull-up node and a signal inputted from the first signal terminal; a pull-down control sub-circuit coupled to a first node, a second signal terminal, and a pull-down node, configured to conduct the pull-down node with the first node under control of a signal inputted from the second signal terminal; a pull-down sub-circuit coupled to the pull-up node, the pull-down node, the first node, a turn-down signal terminal, and the output terminal, configured to conduct the pull-up node with the first node, and to conduct the turn-down signal terminal with the output terminal, under control of a potential of the pull-down node; and a voltage regulating sub-circuit coupled to the first node and the turn-down signal terminal, configured to conduct the first node with the turn-down signal terminal under control of a potential of the first node.

2 . The shift register unit circuit of claim 1 , further comprising a reset sub-circuit, coupled to a reset terminal, the pull-up node, the first node, the output terminal, and the turn-down signal terminal, configured to conduct the turn-down signal terminal with the output terminal and to conduct the first node with the pull-up node under control of a signal inputted from the reset terminal.

3 . The shift register unit circuit of claim 1 , wherein the voltage regulating sub-circuit comprises a voltage regulating transistor, wherein:
a first electrode of the voltage regulating transistor is coupled to the turn-down signal terminal; a second electrode and a gate electrode of the voltage regulating transistor are coupled to each other and are both coupled to the first node.

4 . The shift register unit circuit of claim 3 , wherein a width-length ratio of a channel of the voltage regulating transistor is larger than or equal to two.

5 . The shift register unit circuit of claim 1 , wherein the voltage regulating sub-circuit comprises a diode, wherein:
an anode of the diode is coupled to the first node; and a cathode of the diode is coupled to the turn-down signal terminal.

6 . The shift register unit circuit of claim 1 , wherein the input sub-circuit comprises an input transistor having a gate electrode, a first electrode and a second electrode, wherein:
the gate electrode and the first electrode of the input transistor are coupled to each other and are both coupled to the signal input terminal; and the second electrode of the input transistor is coupled to the pull-up node.

7 . The shift register unit circuit of claim 6 , wherein the input sub-circuit further comprises a filter transistor wherein:
a first electrode of the filter transistor is coupled to the first electrode of the input transistor; a second electrode of the filter transistor is coupled to the second electrode of the input transistor; and a gate electrode of the filter transistor is coupled to the second signal terminal.

8 . The shift register unit circuit of claim 1 , wherein the pull-up sub-circuit comprises a pull-up transistor and a storage unit, wherein:
a gate electrode of the pull-up transistor is coupled to the pull-up node, a first electrode of the pull-up transistor is coupled to the first signal terminal, and a second electrode of the pull-up transistor is coupled to the output terminal; and one terminal of the storage unit is coupled to the gate electrode of the pull-up transistor, and another terminal of the storage unit is coupled to the second electrode of the pull-up transistor.

9 . The shift register unit circuit of claim 8 , wherein the storage unit comprises a capacitor.

10 . The shift register unit circuit of claim 1 , wherein the pull-down sub-circuit comprises a first pull-down transistor and a second pull-down transistor;
a gate electrode of the first pull-down transistor is coupled to the pull-down node, a first electrode of the first pull-down transistor is coupled to the output terminal, and a second electrode of the first pull-down transistor is coupled to the turn-down signal terminal; and a gate electrode of the second pull-down transistor is coupled to the pull-down node, a first electrode of the second pull-down transistor is coupled to the pull-up node, and a second electrode of the second pull-down transistor is coupled to the first node.

11 . The shift register unit circuit of claim 10 , wherein the pull-down sub-circuit further comprises a third pull-down transistor, wherein:
a gate electrode of the third pull-down transistor is coupled to the second signal terminal; a first electrode of the third pull-down transistor is coupled to the first electrode of the first pull-down transistor; and a second electrode of the third pull-down transistor is coupled to the second electrode of the first pull-down transistor.

12 . The shift register unit circuit of claim 1 , wherein the pull-down control sub-circuit comprises a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, and a fourth pull-down control transistor, wherein:
a gate electrode of the first pull-down control transistor is coupled to the second signal terminal, a first electrode of the first pull-down control transistor is coupled to the gate electrode of the first pull-down control transistor, and a second electrode of the first pull-down control transistor is coupled to a first electrode of the third pull-down control transistor; a gate electrode of the second pull-down control transistor is coupled to the second electrode of the first pull-down control transistor, a first electrode of the second pull-down control transistor is coupled to the first electrode of the first pull-down control transistor, and a second electrode of the second pull-down control transistor is coupled to the pull-down node; a gate electrode of the third pull-down control transistor is coupled to the pull-up node, and a second electrode of the third pull-down control transistor is coupled to the first node; and a gate electrode of the fourth pull-down control transistor is coupled to the gate electrode of the third pull-down control transistor, a first electrode of the fourth pull-down control transistor is coupled to pull-down node, and a second electrode of the fourth pull-down control transistor is coupled to the first node.

13 . The shift register unit circuit of claim 2 , wherein the reset sub-circuit comprises a first reset transistor and a second reset transistor, wherein:
a first electrode of the first reset transistor is coupled to the output terminal, a second electrode of the first reset transistor is coupled to the turn-down signal terminal, and a gate electrode of the first reset transistor is coupled to the reset terminal; and a gate electrode of the second reset transistor is coupled to the gate electrode of the first reset transistor, a first electrode of the second reset transistor is coupled to the pull-up node, and a second electrode of the second reset transistor is coupled to the first node.

14 . The shift register unit circuit of claim 1 , wherein:
the first signal terminal is configured to provide a low-level signal during an input stage, a high-level signal during an output stage, and a low-level signal during a pull-

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Qian Xianrui
• Wang Guolei
• Yang Tong
• Mu Suzhen
• Chen Peng
• Chen Yuting
• Wang Zixuan
• Li Bo

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G11C7/1036 Primary

  using data shift registers · CPC title

• G11C7/1051

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title