Unified Addressable Memory

Patent metadata

Field	Value
Publication number	US-2020257829-A1
Application number	US-202016859634-A
Country	US
Kind code	A1
Filing date	Apr 27, 2020
Priority date	Sep 29, 2015
Publication date	Aug 13, 2020
Grant date	—

Abstract

In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.

First claim

What is claimed is:

1 . A system comprising:
a non-volatile memory; and a system on a chip (SOC) coupled to the non-volatile memory, the SOC including:
one or more agents configured to generate memory operations that address locations in the non-volatile memory, the locations forming a main memory in the system;
a link control circuit coupled to the one or more agents and configured to access the locations in the non-volatile memory responsive to the memory operations; and
translation hardware coupled to the one or more agents and the link control circuit, wherein the translation hardware is configured to translate a virtual address generated by a given agent of the one or more agents for a given memory operation to a first physical address, wherein the translation is specified via a first translation data structure that includes data that translates the virtual address to a second physical address and a second translation data structure that includes data that translates the second physical address to the first physical address, and wherein a first page size in the first translation data structure differs from a second page size in the second translation data structure.

2 . The system as recited in claim 1 wherein the first page size is less than the second page size.

3 . The system as recited in claim 1 wherein the second page size matches a third page size implemented by the non-volatile memory.

4 . The system as recited in claim 1 further comprising a cache control circuit configured to cache data from the non-volatile memory, wherein the cache is addressed by the first physical address.

5 . The system as recited in claim 1 further comprising a cache control circuit configured to cache data from the non-volatile memory, wherein the cache is addressed by the second physical address.

6 . The system as recited in claim 1 , wherein data in the main memory is non-persistent with each power down/power up cycle of the system, and wherein the system further comprises a cryptographic circuit coupled to the one or more agents and the link control circuit, wherein the cryptographic circuit is configured to employ one or more keys for encryption or decryption of the data in the main memory, and wherein the SOC is configured to implement the non-persistent nature of the main memory by discarding the one or more keys responsive to a power down/power up cycle.

7 . The system as recited in claim 6 wherein the non-volatile memory is divided into a first portion forming the main memory and a second portion that is defined to be a persistent storage, and wherein the persistent storage is managed by a file system executed on the SOC.

8 . The system as recited in claim 6 wherein a portion of the non-volatile memory is persistent storage, and wherein the data in the persistent storage is encrypted using one or more second keys separate from the one or more keys, and wherein the SOC is configured to retain the one or more second keys in a metadata area of the non-volatile memory.

9 . The system as recited in claim 8 wherein the metadata area further stores initial vectors for use in the encryption or decryption of the data in the persistent storage.

10 . The system as recited in claim 8 wherein the SOC further comprises a metadata cache configured to cache data from the metadata area.

11 . The system as recited in claim 6 wherein the SOC is configured to generate the one or more keys randomly during a power up event in the system.

12 . A method comprising:
generating memory operations that address locations in a non-volatile memory by one or more agents in a system on a chip (SOC), the locations forming a main memory in a system that includes the SOC; accessing the locations in the non-volatile memory responsive to the memory operations by a link control circuit coupled to the non-volatile memory and the one or more agents; and translating a virtual address generated by a given agent of the one or more agents for a given memory operation to a first physical address by translation hardware in the system, wherein the translation is specified via a first translation data structure that includes data that translates the virtual address to a second physical address and a second translation data structure that includes data that translates the second physical address to the first physical address, and wherein a first page size in the first translation data structure differs from a second page size in the second translation data structure.

13 . The method as recited in claim 12 wherein the first page size is less than the second page size.

14 . The method as recited in claim 12 wherein the second page size matches a third page size implemented by the non-volatile memory.

15 . The method as recited in claim 12 further comprising caching data from the non-volatile memory in cache, wherein the cache is addressed by the first physical address.

16 . The method as recited in claim 12 further comprising caching data from the non-volatile memory in cache, wherein the cache is addressed by the first physical address. by the second physical address.

17 . A system comprising:
a non-volatile memory; and a system on a chip (SOC) coupled to the non-volatile memory, the SOC including:
one or more agents configured to generate memory operations that address locations in the non-volatile memory, the locations forming a main memory in the system, and wherein data in the main memory is non-persistent with each power down/power up cycle of the system;
a link control circuit coupled to the one or more agents and configured to access the locations in the non-volatile memory responsive to the memory operations; and
a cryptographic circuit coupled to the one or more agents and the link control circuit, wherein the cryptographic circuit is configured to employ one or more keys for encryption of data in the main memory, and wherein the SOC is configured to discard the one or more keys to implement the non-persistent nature of the main memory at a power down of the SOC.

18 . The system as recited in claim 17 wherein a portion of the non-volatile memory is persistent storage, and wherein the data in the persistent storage is encrypted using one or more second keys separate from the one or more keys, and wherein the SOC is configured to retain the one or more second keys in a metadata area of the non-volatile memory.

19 . The system as recited in claim 18 wherein the metadata area further stores initial vectors for use in the encryption or decryption of the data in the persistent storage.

20 . The system as recited in claim 18 wherein the SOC is configured to generate the one or more keys randomly during a power up in the system.

Assignees

• Apple Inc

Inventors

• Gulati Manu
• Sokol Jr Joseph
• Wilcox Jeffrey R
• Semeria Bernard J
• Smith Michael J

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F2221/2143

  Clearing memory, e.g. to prevent the data from being stolen · CPC title

• G06F2212/7208

  Multiple device management, e.g. distributing data over multiple flash devices · CPC title

• G06F2212/7206

  Reconfiguration of flash memory system · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title