Two-wire communication systems and applications

Patent metadata

Field	Value
Publication number	US-2020257646-A1
Application number	US-202016859611-A
Country	US
Kind code	A1
Filing date	Apr 27, 2020
Priority date	Oct 5, 2011
Publication date	Aug 13, 2020
Grant date	—

Abstract

Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

First claim

What is claimed is:

1 . Entertainment equipment with low-latency communication capability, comprising:
an audio device; and a node transceiver, including:
upstream transceiver circuitry to receive a first signal transmitted over two upstream wires of a two-wire bus from an upstream equipment and to provide a second signal over the two upstream wires of the two-wire bus to the upstream equipment;
clock circuitry to generate a clock signal at the node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal;
power circuitry to receive a voltage bias between the two upstream wires of the two-wire bus from the upstream equipment; and
interface circuitry to communicate with the audio device.

Assignees

• Analog Devices Inc

Inventors

• Kessler Martin
• Chavez Miguel A
• Lahr Lewis F
• Hooper William
• Adams Robert
• Sealey Peter

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F13/426 Primary

  using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• H04R29/007

  for public address systems (public address systems per se H04R27/00) · CPC title

• G05B19/0421

  Multiprocessor system · CPC title