Clamp for power transistor device

Patent metadata

Field	Value
Publication number	US-2020251465-A1
Application number	US-201916264065-A
Country	US
Kind code	A1
Filing date	Jan 31, 2019
Priority date	Jan 31, 2019
Publication date	Aug 6, 2020
Grant date	—

Abstract

A system includes a clamp network coupled between an input and an output and configured to clamp a voltage between the input and the output to a first clamp voltage based on the presence of a trigger signal and to a second clamp voltage based on the absence of the trigger signal. The second clamp voltage is greater than the first clamp voltage and the first clamp voltage is less than a breakdown voltage of the power transistor device. A detector circuit is coupled to the input and the output. A power transistor device may also be coupled between the input and the output. The detector circuit is configured to detect a pulse signal at the input or the output while the power transistor device is off and to generate the trigger signal for a time interval based on detecting the pulse signal.

First claim

What is claimed is:

1 . A clamp device comprising:
a detector circuit having an input and an output configured to be coupled, respectively, to an input and an output of a switch device, the detector circuit including a first detector circuit configured to generate a trigger signal for a period of time based on detecting a pulse signal provided at the output while the switch device is off, the detector circuit including a second detector circuit configured to activate the first detector circuit to generate the trigger signal based on detecting a pulse signal provided at the input while the switch device is off; and a clamp network configured to clamp a voltage between the input and the output to a first clamp voltage in response to the trigger signal and to a second clamp voltage in the absence of the trigger signal while the switch device is off, the second clamp voltage being greater than the first clamp voltage and the first clamp voltage being greater than a predetermined supply voltage at the input.

2 . The clamp device of claim 1 , wherein the first detector circuit further comprises:
a filter coupled to the output and configured to filter the detected pulse signal at the output and to provide a filtered pulse signal; and a timer circuit configured to provide the trigger signal for a duration based on the filtered pulse signal.

3 . The clamp device of claim 2 , wherein the first detector circuit further comprises a switch network coupled between the input and an intermediate node of the clamp network, the switch network configured to connect the intermediate node to the input in response to the trigger signal to reduce the clamp voltage to the first clamp voltage.

4 . The clamp device of claim 2 , wherein the second detector circuit further comprises:
a filter coupled to the input and configured to filter the detected pulse signal at the input and to provide a respective filtered pulse signal; and a timer circuit configured to activate the timer circuit of the first detector circuit based on the respective filtered pulse signal.

5 . The clamp device of claim 2 , wherein each of the filters comprises a respective high pass filter to buffer the respective voltage, and
wherein each of the timer circuits comprises a resistor-capacitor network to hold the trigger signal for the duration.

6 . The clamp device of claim 1 , wherein the clamp network comprises a plurality of diodes connected in series between the input and the output, the first detector circuit being configured to connect the input to a node between an adjacent pair of the plurality of diodes in response to the trigger signal to reduce the clamp voltage to the first clamp voltage according to a sum of breakdown voltages of the diodes connected between the node and the output.

7 . The clamp device of claim 1 , wherein the second clamp voltage is greater than a load dump voltage and less than a breakdown voltage of the switch device.

8 . The clamp device of claim 1 , wherein during a transition from when the switch device operates in an on state to an off state, the detector circuit is configured to activate the clamp network to the first clamp voltage for a time interval that is longer than required for output current to reach zero.

9 . The clamp device of claim 1 , further including the switch device coupled between the input and the output, the switch device comprising a field effect transistor having a drain coupled to the input and a source coupled to the output, the first clamp voltage being less than a breakdown voltage of the field effect transistor.

10 . The clamp device of claim 9 , wherein a gate of the field effect transistor is coupled to the clamp network, a resistor being coupled between the gate and the source of the field effect transistor.

11 . The circuit of claim 1 , wherein at least the detector circuit and the clamp network are on a common substrate of an integrated circuit chip.

12 . A clamp circuit, comprising:
a clamp network including a plurality of diodes connected in series between an input voltage node and an output voltage node; a first detector circuit coupled between the input voltage node and the output voltage node, the first detector circuit having an input coupled to the output voltage node, the first detector including a switch network coupled between the input voltage node and an intermediate node of the clamp network between an adjacent pair of the plurality of diodes; and a second detector circuit having an input coupled to the input voltage node and an output coupled to a control input of the first detector circuit.

13 . The circuit of claim 12 , wherein the clamp network is configured to clamp a voltage between the input voltage node and the output voltage node to a first clamp voltage in response to a trigger signal turning on the switch network to couple the intermediate node to the input voltage node, bypassing each of the diodes between the input voltage node and the intermediate node, and to a second clamp voltage while the switch network is turned off in the absence of the trigger signal, each of the first and second clamp voltages being based on a sum of breakdown voltages of the diodes connected in the path between the input voltage node and the output voltage node, and the second clamp voltage being greater than the first clamp voltage.

14 . The circuit of claim 12 , wherein the first detector circuit further comprises:
a filter circuit coupled between the input voltage node and the output voltage node configured to filter a detected pulse signal at the output voltage node and to provide a filtered pulse signal; and a timer circuit coupled to the filter circuit and configured to provide a trigger signal to activate the switch network for a duration based on the filtered pulse signal.

15 . The circuit of claim 14 , wherein the second detector circuit further comprises:
a filter having an input coupled to the input voltage node, the filter of the second detector circuit being configured to provide a respective filtered pulse signal filter based on receiving a pulse signal at the input voltage node; and a timer circuit configured to control a switch device, which is coupled to the control input of the first detector circuit, based on the respective filtered pulse signal.

16 . The circuit of claim 15 , wherein the filter of the first detector circuit further comprises a respective high pass filter configured to buffer the pulse signal at the output voltage node, and
wherein the timer circuit of the first detector circuit comprises a resistor-capacitor network to sustain the trigger signal for a period of time.

17 . The circuit of claim 12 , further comprising a power transistor device coupled between the input voltage node and the output voltage node, the power transistor device including a control input node, a resistor being coupled between the control input node and the output voltage node.

18 . The circuit of claim 17 , wherein the power transistor device comprises a field effect transistor having a drain coupled to the input voltage node and a source coupled to the output voltage node and a gate coupled to control input node, the first clamp voltage being less than a breakdown voltage of the field effect transistor.

19 . A system comprising:
a power transistor device coupled between an input and an output; a clamp network coupled between the input and the output and configured to clamp a voltage between the input and the output to a first clamp voltage based on the presence of

Assignees

• Texas Instruments Inc

Inventors

• Kim Eung Jung
• Schulmeyer Kyle Clifton
• Aras Sualp
• Rahman Md Abidur
• Zhao Xiaochun

Classifications

• H10D89/819

  Bias arrangements for gate electrodes of FETs, e.g. RC networks or voltage partitioning circuits (FETs in a Darlington configuration H10D89/817) · CPC title

• H10D89/611 Primary

  using diodes as protective elements · CPC title

• H02M1/32

  Means for protecting converters other than automatic disconnection · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H03K17/0822 Primary

  in field-effect transistor switches · CPC title