Power semiconductor device and manufacturing method for power semiconductor device

Patent metadata

Field	Value
Publication number	US-2020251423-A1
Application number	US-201816647886-A
Country	US
Kind code	A1
Filing date	Oct 25, 2018
Priority date	Oct 30, 2017
Publication date	Aug 6, 2020
Grant date	—

Abstract

A power semiconductor device includes a substrate and a semiconductor element bonded onto a first surface of the substrate through use of a sintered metal bonding material. The substrate has a plurality of dimples formed in the first surface and located outside a location immediately below a heat generation unit of the semiconductor element. The sintered metal bonding material is supplied onto the substrate after the formation of the dimples, and the semiconductor element is bonded to the substrate through application of heat and a pressure thereto.

First claim

1 - 10 . (canceled)

11 . A power semiconductor device, comprising:
a substrate; and a semiconductor element bonded onto a first surface of the substrate through use of a sintered metal bonding material, the substrate having, in the first surface, a first region immediately below a heat generation unit of the semiconductor element and a second region including a region located immediately below the semiconductor element and outside the first region and a region located outside an end portion of the semiconductor element, the first region and the second region having different surface roughnesses, the second region having dimples formed by laser processing.

12 . The power semiconductor device according to claim 11 , wherein the heat generation unit of the semiconductor element is located in a region on an inner side of a guard ring of the semiconductor element in plan view.

13 . The power semiconductor device according to claim 11 , wherein the dimples are formed in the first surface to extend to a location outside a region of the first surface in which the substrate and the semiconductor element are bonded to each other.

14 . The power semiconductor device according to claim 11 , wherein the dimples are formed to be arranged in a linear shape in parallel with an outer shape of the semiconductor element.

15 . The power semiconductor device according to claim 11 , wherein silicon is used as a material of the semiconductor element.

16 . The power semiconductor device according to claim 11 , wherein the first region of the substrate is a surface having a roughness equal to or less than 0.5 μm.

17 . A manufacturing method for a power semiconductor device that includes a semiconductor element bonded onto a first surface of a substrate through use of a sintered metal bonding material, the manufacturing method comprising:
a first step of forming, by laser processing in the first surface of the substrate, a plurality of dimples each of which has a surface roughness of from 0.5 μm to 10 μm and is located outside a location immediately below a heat generation unit of the semiconductor element; a second step of supplying a sintered metal bonding material onto the substrate after the formation of the plurality of dimples; a third step of supplying the semiconductor element onto the sintered metal bonding material; and a fourth step of applying heat and a pressure to the semiconductor element on the sintered metal bonding material to bond the semiconductor element onto the first surface by sintered metal bonding.

18 . The manufacturing method for the power semiconductor device according to claim 17 , wherein a time period after the first step and before execution of the second step is equal to or less than 10,000 seconds.

19 . A manufacturing method for a power semiconductor device that includes a semiconductor element bonded onto a first surface of a substrate through use of a sintered metal bonding material, the manufacturing method comprising:
a first step of forming, in the first surface of the substrate, a plurality of dimples each of which has a surface roughness of from 0.5 μm to 10 μm and is located outside a location immediately below a heat generation unit of the semiconductor element; a second step of removing an oxide film lying on a top of a region of the first surface which is located immediately below the heat generation unit of the semiconductor element through use of a laser; a third step of supplying a sintered metal bonding material onto the substrate after the formation of the plurality of dimples and the newly formed surface; a fourth step of supplying the semiconductor element onto the sintered metal bonding material; and a fifth step of applying heat and a pressure to the semiconductor element on the sintered metal bonding material to bond the semiconductor element onto the first surface by sintered metal bonding.

20 . The manufacturing method for the power semiconductor device according to claim 19 , wherein the first step and the second step are executed by the same step.

21 . The manufacturing method for the power semiconductor device according to claim 19 , wherein a time period after completion of the first step or completion of the second step and before the supply of the sintered metal bonding material is equal to or less than 10,000 seconds.

Assignees

• Mitsubishi Electric Corp

Inventors

• Yabuta Kohei
• Yamada Takayuki
• Muramatsu Yuya
• Besshi Noriyuki
• Sugi Yutaro
• Haruna Hiroaki
• Fuku Masaru
• Fujita Atsuki

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W72/07331

  Connecting techniques · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/931

  Shapes of bond pads · CPC title

• H10W72/07332

  Compression bonding, e.g. thermocompression bonding · CPC title