Systems, methods and devices for high-speed input/output margin testing

Patent metadata

Field	Value
Publication number	US-2020250368-A1
Application number	US-202016778249-A
Country	US
Kind code	A1
Filing date	Jan 31, 2020
Priority date	Jan 31, 2019
Publication date	Aug 6, 2020
Grant date	—

Abstract

Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link of a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

First claim

1 . A test device, comprising:
one or more printed circuit boards (PCBs); at least one interface coupled to the one or more PCBs; and a controller coupled to the at least one interface, the controller configured to establish a single-lane or multi-lane high speed input/output (I/O) link of a device under test (DUT) and to cause the test device to assess an electrical margin of the single-lane or multi-lane high speed I/O link in either or both transmit (Tx) and receive (Rx) directions.

2 . The test device of claim 1 wherein the at least one interface comprises at least one lane configured to be connected to at least one test fixture to assess the electrical margin of the single-lane or multi-lane high speed I/O link of the DUT in either or both Tx and Rx directions.

3 . The test device of claim 2 wherein the at least one lane comprises a plurality of lanes, and wherein the controller is configured to support multiple different protocols for the test device to test multiple different devices that each operate according to a different protocol, and to provide options to configure the plurality of lanes for different device roles and the multiple different protocols.

4 . The test device of claim 3 wherein the plurality of lanes is configured to be connected to at least one test fixture to assess an electrical margin of a multi-lane high speed I/O link of one or more of: a motherboard and an add-in card.

5 . The test device of claim 3 wherein the plurality of lanes is configured to be connected to test fixtures to assess electrical margins of multi-lane high speed I/O links of at least one motherboard and of at least one add-in card.

6 . The test device of claim 4 wherein the at least one test fixture includes one or more of: a Peripheral Component Interconnect Express (PCI Express) Compliance Load Board (CLB) and a PCI Express Compliance Base Board (CBB).

7 . The test device of claim 1 wherein the single-lane or multi-lane high speed I/O link of the DUT is a fully running operational link without a special test mode.

8 . The test device of claim 1 wherein the one or more PCBs includes a PCB of an add-in card and the DUT is a motherboard, the add-in card configured to be plugged into a connector on the motherboard to implement physical and link logical layers for each lane of the single-lane or multi-lane high speed I/O link.

9 . The test device of claim 8 wherein the add-in card is a PCI Express add-in card.

10 . The test device of claim 1 wherein the controller is configured to assess the electrical margin of the single-lane or multi-lane high speed I/O link by at least being configured to inject adjustable stress on margin test transmitters, the adjustable stress including one or more of: reduction of eye width opening and reduction of eye height opening.

11 . The test device of claim 10 wherein the controller is configured to assess the electrical margin of the single-lane or multi-lane high speed I/O link by at least being configured to inject reduction of eye width opening by injecting jitter on margin test transmitters, the injection of jitter being selectable to be applied on all lanes of the single-lane or multi-lane high speed I/O link simultaneously or applied independently per lane of the of the single-lane or multi-lane high speed I/O link.

12 . The test device of claim 10 wherein the controller is configured to assess the electrical margin of the single-lane or multi-lane high speed I/O link by at least being configured to inject reduction of eye height opening by injecting noise on margin test transmitters, the injection of noise being selectable to be applied on all lanes of the single-lane or multi-lane high speed I/O link simultaneously or applied independently per lane of the of the single-lane or multi-lane high speed I/O link.

13 . The test device of claim 10 wherein the controller is configured to assess the electrical margin of the single-lane or multi-lane high speed I/O link by at least being configured to inject reduction of eye width and eye height opening by injecting differential noise on margin test transmitters, the injection of differential noise being selectable to be applied on all lanes of the single-lane or multi-lane high speed I/O link simultaneously or applied independently per lane of the of the single-lane or multi-lane high speed I/O link.

14 . A method for electrical margin testing a device under test (DUT), the method comprising:
establishing, by a test device, a multi-lane high speed I/O link of the DUT; and assessing, by the test device, an electrical margin, in either or both transmit (Tx) and receive (Rx) directions, for each high-speed input/output (I/O) lane of the multi-lane high speed I/O link.

15 . The method of claim 14 wherein the assessing the electrical margin includes injecting adjustable stress on margin test transmitters of the multi-lane high speed I/O link, the adjustable stress including injection of jitter or other method of eye width closing applied on all lanes of the multi-lane high speed I/O link simultaneously or applied independently per lane and applying noise or other method of eye height reduction.

16 . The method of claim 15 wherein the assessing the electrical margin includes assessing the electrical margin, in either or both Tx and Rx directions, simultaneously for each high-speed I/O lane of the multi-lane high speed I/O link.

17 . The method of claim 14 wherein the assessing the electrical margin includes:
assessing, by the test device, for each DUT of a plurality of devices under test (DUTs), timing eye width margin, in either or both Tx and receive Rx directions, for each high-speed I/O lane of a multi-lane high speed I/O link of the DUT;
detecting, based on the assessing, timing eye width margin measurements for each DUT of the plurality of DUTs that are consistently below a predetermined threshold for a same lane across the plurality of DUTs; and
identifying a potential DUT design issue based on the detection of the eye width and/or eye height margin measurements for each DUT of the plurality of DUTs that are consistently below the predetermined threshold for the same lane across the plurality of DUTs.

18 . The method of claim 14 wherein the assessing the electrical margin includes:
assessing, by the test device, for each DUT of a plurality of DUTs, eye width and/or eye height margin, in either or both Tx and Rx directions, for each high-speed I/O lane of a multi-lane high speed I/O link of the DUT;
detecting, based on the assessing, timing eye width margin measurements for multiple DUTs of the plurality of DUTs that are each below a predetermined threshold for different lanes across the multiple DUTs; and
identifying a potential DUT assembly or production issue based on the detection of the timing eye width margin measurements for the multiple DUTs that are each below the predetermined threshold for different lanes across the multiple DUTs.

19 . A non-transitory computer-readable storage medium having computer-executable instructions stored thereon that, when executed, cause at least one processor to:
provide user-selectable options for a test device that is configured to establish a multi-lane high speed input/output (I/O) link of a device under test (DUT) and to assess an electrical margin of the multi-lane high speed I/O link in either or both transmit (Tx) and receive (Rx) directions, the user-selectable options including customizations for assessment of the electrical margin of the multi-lane high speed I/O link; rece

Assignees

• Tektronix Inc

Inventors

• Froelich Daniel S
• Hazzard Shane A
• Boen Sarah R
• Andrews Jed H

Classifications

• G06F13/4068

  Electrical coupling · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• H04L43/50

  Testing arrangements · CPC title

• G06F11/273 Primary

  Tester hardware, i.e. output processing circuits {(G06F11/263 takes precedence)} · CPC title

• G01R31/31715 Primary

  Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer · CPC title