Systems, methods and devices for high-speed input/output margin testing

Patent metadata

Field	Value
Publication number	US-2020249275-A1
Application number	US-202016778262-A
Country	US
Kind code	A1
Filing date	Jan 31, 2020
Priority date	Jan 31, 2019
Publication date	Aug 6, 2020
Grant date	—

Abstract

Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link of a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

First claim

1 . A margin tester, comprising:
a motherboard; and at least one slot coupled to the motherboard to margin test at least one add-in card, wherein the motherboard is configured to assess an electrical margin of a multi-lane high speed input/output (I/O) link of the add-in card in either or both transmit (Tx) and receive (Rx) directions after the add-in card is inserted into the at least one slot.

2 . The margin tester of claim 1 wherein the multi-lane high speed I/O link of the add-in card is a fully running operational link without a special test mode.

3 . The margin tester of claim 1 wherein the motherboard is configured to assess the electrical margin of the multi-lane high speed I/O link by at least being configured to:
inject controlled noise on margin test transmitters; and
vary an eye margin expected at a receiver of the motherboard to specific targets for timing or voltage margin.

4 . The margin tester of claim 1 wherein the motherboard is configured to assess the electrical margin of the multi-lane high speed I/O link by at least being configured to:
inject jitter on margin test transmitters; and
vary an eye margin expected at a receiver of the motherboard to specific targets for timing or voltage margin.

5 . The margin tester of claim 1 wherein the motherboard is configured to assess the electrical margin of the multi-lane high speed I/O link by at least being configured to cause margin test receivers to measure eye margin by moving an independent error detector and comparing for mismatches with a data sampler.

6 . The margin tester of claim 1 wherein the motherboard is configured to provide different margin test modes to enable problem characterization of the add-in card based on margin test measurements.

7 . The margin tester of claim 1 wherein the motherboard is configured to assess the electrical margin of the multi-lane high speed I/O link by at least being configured to inject reduction of eye width and eye height opening by injecting differential noise on margin test transmitters, the injection of differential noise being selectable to be applied on all lanes of the multi-lane high speed I/O link simultaneously or applied independently per lane of the of the multi-lane high speed I/O link.

8 . The margin tester of claim 1 wherein the motherboard is configured to assess the electrical margin of the multi-lane high speed I/O link by at least being configured to inject jitter on margin test transmitters, the injection of jitter being selectable to be applied on all lanes of the multi-lane high speed I/O link simultaneously or applied independently per lane of the of the multi-lane high speed I/O link.

9 . The margin tester of claim 8 wherein the injection of jitter is selectable to be applied on all lanes of the multi-lane high speed I/O link simultaneously or applied independently per lane of the of the multi-lane high speed I/O link.

10 . The margin tester of claim 8 wherein the motherboard is configured to inject jitter on margin test transmitters by at least being configured to modulate an electrical length of a signal path to effect a jitter characteristic relative to an assumed ideal constant timing fiducial.

11 . The margin tester of claim 8 wherein the motherboard is configured to inject jitter on margin test transmitters using a varactor-based method.

12 . A method, comprising:
calibrating a margin tester, enabling a user to receive a set of expected margins with a series of reference channels; and providing the calibrated margin tester configured to measure electrical eye margin in either or both transmit (Tx) and receive (Rx) directions of a device under test (DUT) with a fully running operation link of the DUT without special test modes and to capture full loading and cross-talk effects.

13 . The method of claim 12 , further comprising:
providing an individually calibrated model for the margin tester, enabling computation of expected margins with one or more of: individualized system channels, receiver models and transmitter models.

14 . The method of claim 12 , further comprising:
providing a software plug-in model in a configuration software application for the margin tester, enabling silicon vendors to provide software plug-ins that enable configuration and DUT silicon parameters for running margin tests by the margin tester under different conditions for the DUT silicon.

15 . The method of claim 12 , further comprising:
providing a feature in DUT silicon, enabling the margin tester to use vendor defined messages or another protocol mechanism to indicate that a margin test is about to take place by the margin tester, causing the DUT silicon to be able to disable logic that would degrade link width or speed of the link due to errors for a duration of the margin test.

16 . The method of claim 12 , further comprising:
providing a software applications of the margin tester, enabling performance of testing by the margin tester of a channel component under test in a testing configuration where a margin tester is used on both sides of the channel component under test.

17 . The method of claim 16 wherein the channel component under test is a bare printed circuit board (PCB) or a cable.

18 . The method of claim 12 , further comprising:
providing hardware of the margin tester to a company that manufactures a printed circuit board (PCB); and providing data associated with use of the margin tester to silicon companies which provide silicon used in production of the PCB.

19 . A non-transitory computer-readable storage medium having computer-executable instructions stored thereon that, when executed, cause at least one processor to:
receive configuration settings for a device under test (DUT); and configure the DUT for running margin tests by a margin tester under different conditions for silicon of the DUT.

20 . The non-transitory computer-readable storage medium of claim 18 wherein the computer-executable instructions, when executed, cause the at least one processor to cause the margin tester to do one or more of:
receive a software plug-in that enables configuration and DUT silicon parameters for running the margin tests by the margin tester under the different conditions for the silicon of the DUT.

21 . The non-transitory computer-readable storage medium of claim 20 wherein the DUT silicon parameters include one or more of: parameters related to receiver continuous time linear equalization (CTLE) and parameters related to decision feedback equalization (DFE).

Assignees

• Tektronix Inc

Inventors

• Froelich Daniel S
• Hazzard Shane A
• Boen Sarah R
• Andrews Jed H

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F2213/0026

  PCI express · CPC title

• G06F13/20

  for access to input/output bus · CPC title

• G01R31/31715 Primary

  Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer · CPC title