Reducing coupling and power noise on pam-4 i/o interface

Patent metadata

Field	Value
Publication number	US-2020242062-A1
Application number	US-201915929094-A
Country	US
Kind code	A1
Filing date	Jan 28, 2019
Priority date	Jan 28, 2019
Publication date	Jul 30, 2020
Grant date	—

Abstract

Methods of operating a serial data bus divide series of data bits into sequences of one or more bits and encode the sequences as N-level symbols, which are then transmitted at multiple discrete voltage levels. These methods may be utilized to communicate over serial data lines to improve bandwidth and reduce crosstalk and other sources of noise.

First claim

What is claimed is:

1 . A method of encoding a series of data bits comprising:
dividing the series of data bits into sequences of a number of bits, the number of bits based on a number of voltage levels, N, utilized in a PAM-N symbol; encoding a first number of bits of each of the sequences as an N-level symbol, the first number of bits being the base-2 logarithm of N; encoding a next number of bits of each of the sequences as two M-level symbols, the next number of bits being log 2 [(N{circumflex over ( )}2)/2] and M being an integer equal to a ceiling function applied to a square root of [(N{circumflex over ( )}2)/2]; and communicating the N-level symbol and the two M-level symbols on a serial data bus.

2 . A method of operating a serial data bus, the method comprising:
dividing a series of data bits for communication on the serial data bus into a plurality of sequences of five bits each; encoding a first two bits of each of the sequences of five bits on the serial data bus as a four-level symbol; and encoding a next three bits of each of the sequences of five bits on the serial data bus as two three-level symbols.

3 . The method of claim 2 , wherein the two three-level symbols are selected to eliminate a possibility of maximum voltage deltas between four-level symbols on the serial data bus.

4 . The method of claim 2 , further comprising:
selectively encoding a next three bits of each of the sequences of five bits on the serial data bus on condition that the first two bits of each of the sequences of five bits encodes as a four-level symbol at a highest symbol voltage level or a lowest symbol voltage level utilized by the serial data bus.

5 . The method of claim 2 , wherein the two three-level symbols comprise a first three-level symbol and a second three-level symbol, a voltage level of the first three-level symbol being either (a) at most two voltage steps below a voltage level of the four-level symbol, or (b) at most two voltage steps above the voltage level of the four-level symbol.

6 . The method of claim 2 , wherein the two three-level symbols comprise a first three-level symbol and a second three-level symbol, and further comprising:
the sequences of five bits comprising a first sequence of five bits for communication on the serial data bus, and a second sequence of five bits for communication after the first sequence of five bits on the serial data bus; and a voltage level of the second three-level symbol of the first sequence of five bits being either (a) at most two voltage steps below a voltage level of the four-level symbol of the second sequence of five bits, or (b) at most two voltage steps above the voltage level of the four-level symbol of the second sequence of five bits.

7 . A method of operating a serial data bus, the method comprising:
dividing a series of data bits for communication on the serial data bus into sequences of seven bits; encoding a first four bits of each of the sequences of seven bits onto the serial data bus as two four-level symbols; and encoding a next three bits of each of the sequences of seven bits onto the serial data bus as two three-level symbols.

8 . The method of claim 7 , wherein the serial data bus comprises a first data lane and a second data lane, and transmission of the two four-level symbols is staggered in time between the first data lane and the second data lane.

9 . The method of claim 8 , wherein staggering the transmission of the two four-level symbols between the first data lane and the second data lane comprises transmission of two four-level symbols for the first data lane different during a different clock interval than transmission of two four-level symbols for the second data lane.

10 . The method of claim 7 , further comprising:
selectively encoding the next three bits of each of the sequences of seven bits on the serial data bus on condition that a second two bits of each of the sequences of seven bits encodes as a four-level symbol at a highest symbol voltage level or a lowest symbol voltage level utilized by the serial data bus.

11 . The method of claim 7 , wherein the two three-level symbols comprise a first three-level symbol and a second three-level symbol, a voltage level of the first three-level symbol being either (a) at most two voltage steps below a voltage level of a second one of the two four-level symbols, or (b) at most two voltage steps above the voltage level of the second one of the two four-level symbols.

12 . The method of claim 7 wherein the two three-level symbols comprise a first three-level symbol and a second three-level symbol, and further comprising:
the sequences of seven bits comprising a first sequence of seven bits for communication on the serial data bus, and a second sequence of seven bits for communication on the serial data bus after the communication of the first sequence of seven bits on the serial data bus; and
a voltage level of the second three-level symbol of the first sequence of seven bits being either (a) at most two voltage steps below a voltage level of a second one of the two four-level symbols of the first sequence of seven bits, or (b) at most two voltage steps above the second one of the two four-level symbols of the first sequence of seven bits.

13 . A serial data bus transmitter comprising:
a plurality of line driver circuits; logic coupled to the line driver circuits to encode a first two bits of a sequence of five bits as a four-level symbol and encoding a next three bits of each of the sequences of five bits as two three-level symbols.

14 . The serial data bus transmitter of claim 13 , further comprising logic encoding the next three bits as the two three-level symbols on condition that that the first two bits of each of the sequence of five bits encodes as a four-level symbol at a highest voltage level or a lowest voltage level utilized on the serial data bus.

15 . The serial data bus transmitter of claim 13 , wherein the two three-level symbols comprise a first three-level symbol and a second three-level symbol and a voltage level of the first three-level symbol is at most two voltage steps below a voltage level of the four-level symbol.

16 . The serial data bus transmitter of claim 13 , wherein the two three-level symbols comprise a first three-level symbol and a second three-level symbol and a voltage level of the first three-level symbol is at most two voltage steps above the voltage level of the four-level symbol.

17 . The serial data bus transmitter of claim 13 , wherein the two three-level symbols comprise a first three-level symbol and a second three-level symbol; and
the serial data bus transmitter further comprises logic to set a voltage level of the second three-level symbol of a first sequence of five bits to at most two voltage steps below a voltage level of the four-level symbol of a second sequence of five bits.

18 . The serial data bus transmitter of claim 13 , wherein the two three-level symbols comprise a first three-level symbol and a second three-level symbol; and
the serial data bus transmitter further comprises logic to set a voltage level of the second three-level symbol of a first sequence of five bits to at most two voltage steps above a voltage level of the four-level symbol of the second sequence of five bits.

Assignees

• Nvidia Corp

Inventors

• Lee Donghyuk
• O'Connor James Michael

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F13/4045

  where the bus bridge performs an extender function · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4009 Primary

  with data restructuring · CPC title