Neuromorphic arithmetic device and operating method thereof

Patent metadata

Field	Value
Publication number	US-2020226456-A1
Application number	US-202016742808-A
Country	US
Kind code	A1
Filing date	Jan 14, 2020
Priority date	Jan 15, 2019
Publication date	Jul 16, 2020
Grant date	—

Abstract

The neuromorphic arithmetic device comprises an input monitoring circuit that outputs a monitoring result by monitoring that first bits of at least one first digit of a plurality of feature data and a plurality of weight data are all zeros, a partial sum data generator that skips an arithmetic operation that generates a first partial sum data corresponding to the first bits of a plurality of partial sum data in response to the monitoring result while performing the arithmetic operation of generating the plurality of partial sum data, based on the plurality of feature data and the plurality of weight data, and a shift adder that generates the first partial sum data with a zero value and result data, based on second partial sum data except for the first partial sum data among the plurality of partial sum data and the first partial sum data generated with the zero value.

First claim

What is claimed is:

1 . A neuromorphic arithmetic device comprising:
an input monitoring circuit to output a monitoring result by monitoring that first bits of at least one first digit of a plurality of feature data and a plurality of weight data are all zeros; a partial sum data generator to skip an arithmetic operation that generates a first partial sum data corresponding to the first bits of a plurality of partial sum data in response to the monitoring result while performing the arithmetic operation of generating the plurality of partial sum data, based on the plurality of feature data and the plurality of weight data; and a shift adder to generate the first partial sum data with a zero value, and generate result data, based on second partial sum data except for the first partial sum data among the plurality of partial sum data and the first partial sum data generated with the zero value.

2 . The neuromorphic arithmetic device of claim 1 , wherein the input monitoring circuit comprises an OR gate that receives the first bits of the first digit as inputs.

3 . The neuromorphic arithmetic device of claim 1 , wherein the input monitoring circuit comprises a MOSFET for receiving each of the first bits of the first digit through a gate terminal, one end of the MOSFET is connected to a ground voltage and the other end is connected to a power supply voltage.

4 . The neuromorphic arithmetic device of claim 1 , wherein the partial sum data generator comprises:
a multiplication register to generate multiplication bits, based on second bits of a second digit of the plurality of feature data and third bits of a third digit of the plurality of weight data; a digital to analog converter to generate an analog signal corresponding to a sum of the multiplication bits; a sample and hold circuit to sample the analog signal; and an analog to digital converter to convert the sampled analog signal into a digital signal to generate the second partial sum data.

5 . The neuromorphic arithmetic device of claim 4 , wherein the multiplication register multiplies one of the second bits by one of the third bits to generate one of the multiplication bits.

6 . The neuromorphic arithmetic device of claim 4 , wherein the multiplication register is further configured to skip an operation of generating multiplication bits, based on the first bits.

7 . The neuromorphic arithmetic device of claim 4 , wherein at least one of the second bits is 1 and at least one of the third bits is 1.

8 . The neuromorphic arithmetic device of claim 1 , wherein each of the first bits is not a bit representing a sign.

9 . The neuromorphic arithmetic device of claim 1 , wherein the result data corresponds to a convolution result of the plurality of feature data and the plurality of weight data.

10 . A method of operating a neuromorphic arithmetic device, the method comprising:
outputting a monitoring result by monitoring that first bits of at least one first digit of a plurality of feature data and a plurality of weight data are all zeros; skipping an arithmetic operation of generating first partial sum data corresponding to the first bits in response to the monitoring result; processing a value of the first partial sum data to zero; and generating result data based on the first partial sum data that are processed as zero.

11 . The method of claim 10 , further comprising calculating second partial sum data based on second bits of a second digit of the plurality of feature data and third bits of a third digit of the plurality of weight data, and
wherein the result data is generated based on the first partial sum data and the second partial sum data.

12 . The method of claim 11 , wherein the calculating of the second partial sum data comprises:
generating multiplication bits based on the second bits and the third bits; generating an analog signal corresponding to a sum of the multiplication bits; sampling the analog signal; and converting the sampled analog signal into a digital signal to generate the second partial sum data.

13 . The method of claim 11 , wherein at least one of the second bits is 1 and at least one of the third bits is 1.

14 . The method of claim 10 , wherein each of the first bits is not a bit representing a sign.

15 . The method of claim 10 , wherein the result data corresponds to a convolution result of the plurality of feature data and the plurality of weight data.

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• Jeon Young-Deuk
• Kim Byung Jo
• Kim Ju-Yeob
• Kim Jin Kyu
• Park Ki Hyuk
• Lee Mi Young
• Lee Joo Hyun
• Cho Min-Hyung

Classifications

• G06N3/065 Primary

  Analogue means · CPC title

• G06N3/045

  Combinations of networks · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06F17/153

  Multidimensional correlation or convolution · CPC title

• G06F7/57 Primary

  Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)} · CPC title