Memory module with programmable command buffer

Patent metadata

Field	Value
Publication number	US-2020226079-A1
Application number	US-201816631163-A
Country	US
Kind code	A1
Filing date	Oct 17, 2018
Priority date	Oct 24, 2017
Publication date	Jul 16, 2020
Grant date	—

Abstract

A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.

First claim

What is claimed is:

1 . A memory module comprising:
a plurality of memory integrated circuit (IC) packages to store data; and a command buffer IC to buffer one or more memory commands destined for the memory IC packages, the command buffer IC comprising:
a first interface circuit to receive the one or more memory commands; and
one or more second interface circuits to output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.

2 . The memory module of claim 1 , wherein the command buffer IC comprises:
at least one programmable memory to store one or more pre-programmed reference command patterns and to store one or more pre-programmed command sequences; and a pattern matching circuit to determine whether the one or more memory commands match the pre-programmed reference command pattern from the pre-programmed reference command patterns, and a sequence selector circuit to, responsive to the one or more memory commands matching the pre-programmed reference command pattern, select the pre-programmed command sequence from the pre-programmed command sequences, the pre-programmed command sequence associated with the matching pre-programmed reference command pattern.

3 . The memory module of claim 2 , wherein the command buffer IC comprises:
a programming circuit to program the at least one programmable memory with the pre-programmed reference command patterns and the pre-programmed command sequences in response to information received by the command buffer IC.

4 . The memory module of claim 1 , wherein the pre-programmed command sequence output by the one or more second interface circuits comprises at least one command for the plurality of memory IC packages.

5 . The memory module of claim 1 , wherein the pre-programmed command sequence output by the one or more second interface circuits comprises at least one command for a non-volatile memory (NVM) controller circuit.

6 . The memory module of claim 5 , wherein the at least one command for the NVM controller comprises an interrupt command.

7 . The memory module of claim 1 , further comprising:
a plurality of data buffer ICs to buffer data transfers with the memory IC packages; wherein the pre-programmed command sequence output by the one or more second interface circuits comprises at least one command for the data buffer ICs.

8 . The memory module of claim 1 , wherein the first interface circuit is for coupling to a primary command channel, the first interface circuit to receive the one or more memory commands from a memory controller via the primary command channel,
wherein the pre-programmed command sequence is output in response to the one or more memory commands received from the memory controller matching the pre-programmed reference command pattern.

9 . The memory module of claim 1 , wherein the first interface circuit is for coupling to a backup command channel, the first interface circuit to receive the one or more memory commands from a non-volatile memory (NVM) controller via the backup command channel,
wherein the pre-programmed command sequence is output in response to the one or more memory commands received from the NVM controller matching the pre-programmed reference command pattern.

10 . The memory module of claim 1 , wherein the pre-programmed command sequence causes data to be copied from the memory IC packages to non-volatile memory.

11 . The memory module of claim 1 , wherein the command buffer IC comprises an internal functional circuit having a function that is controlled by one or more internal commands triggered responsive to the one or memory commands matching the pre-programmed reference command pattern.

12 . A method of operation in system that comprises a memory module, the memory module comprising a command buffer IC and a plurality of memory IC packages to store data, the method comprising:
buffering, by the command buffer IC, one or more memory commands destined for the memory IC packages; determining, by the command buffer IC, whether the one or more memory commands match a pre-programmed reference command pattern, and responsive to the one or more memory commands matching the pre-programmed reference command pattern, outputting a pre-programmed command sequence from the command buffer IC to one or more devices separate from the command buffer IC.

13 . The method of claim 12 , further comprising:
storing, in the command buffer IC, one or more pre-programmed reference command patterns and pre-programmed command sequences; determining, by the command buffer IC, whether the one or more memory commands match the pre-programmed reference command pattern from the pre-programmed reference command patterns; and selecting the pre-programmed command sequence from the pre-programmed command sequences, the pre-programmed command sequence associated with the matching pre-programmed reference command pattern.

14 . The method of claim 13 , further comprising:
programming the command buffer IC to include the pre-programmed reference command patterns and the pre-programmed command sequences in response to information received by the command buffer IC.

15 . The method of claim 12 , wherein the pre-programmed command sequence comprises at least one command for the plurality of memory IC packages.

16 . The method of claim 12 , wherein the pre-programmed command sequence output comprises at least one command for a non-volatile memory (NVM) controller.

17 . The method of claim 12 , wherein the memory module comprises a plurality of data buffer ICs to buffer data transfers with the memory IC packages;
wherein the pre-programmed command sequence comprises at least one command for the data buffer ICs.

18 . The method of claim 12 further comprising:
receiving, at the command buffer IC, the one or more memory commands from a memory controller via a primary command channel,
wherein the pre-programmed command sequence is output in response to the one or more memory commands received from the memory controller matching the pre-programmed reference command pattern.

19 . The method of claim 12 further comprising:
receiving, at the command buffer IC, the one or more memory commands from a non-volatile memory (NVM) controller via a backup command channel,
wherein the pre-programmed command sequence is output in response to the one or more memory commands received from the NVM controller matching the pre-programmed reference command pattern.

20 . A memory module comprising:
a plurality of data storage means for storing data; and a buffer means for buffering memory commands destined for the plurality of data storage means, determining whether the one or more memory commands match a pre-programmed reference command pattern, and responsive to the one or more memory commands matching the pre-programmed reference command pattern, outputting a pre-programmed command sequence to one or more devices separate from the buffer means.

Assignees

• Rambus Inc

Inventors

• Shallal Aws
• Giddens Larry Grant

Classifications

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G11C7/10 Primary

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G11C2207/104

  Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs · CPC title

• G11C2207/10

  Aspects relating to interfaces of memory device to external buses · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title