Method for fabricating semiconductor device

Patent metadata

Field	Value
Publication number	US-2020219887-A1
Application number	US-201916679317-A
Country	US
Kind code	A1
Filing date	Nov 11, 2019
Priority date	Dec 14, 2018
Publication date	Jul 9, 2020
Grant date	—

Abstract

The instant disclosure discloses method comprising receiving a substrate; disposing a dielectric layer over the substrate; disposing a metallic material on the dielectric layer; disposing a passivation layer on top surface of the metallic material; and performing an alloy layer formation process to dispose a SiGe layer across top surface of the passivation layer.

First claim

What is claimed is:

1 . A method, comprising
receiving a substrate; disposing a dielectric layer over the substrate; disposing a metallic material on the dielectric layer; disposing a passivation layer on top surface of the metallic material; and performing an alloy layer formation process to dispose a SiGe layer across top surface of the passivation layer.

2 . The method of claim 1 , further comprising
disposing, prior to the disposing the dielectric layer, a plurality of lower electrodes over the substrate, wherein each of the lower electrodes has a U-shaped profile in a cross section thereof; wherein the dielectric layer conformally covers the lower electrode; and wherein the metallic material has a substantially planar top surface extends across the lower electrodes and fills in and between the U-shaped profile of the lower electrodes.

3 . The method of claim 2 ,
wherein the disposing the passivation layer comprises supplying a silicon source selectively comprising SiH 4 , BTBAS, BTBAS, and DIPAS to form a silicon film on top surface of the metallic material.

4 . The method of claim 2 ,
wherein the metallic material comprises metal nitrides.

5 . The method of claim 2 ,
wherein the SiGe layer has a Ge concentration distribution that has a greatest value at a middle portion of the SiGe layer and decreases there-from upwardly and downwardly along a thickness direction.

6 . The method of claim 5 ,
wherein the performing the alloy layer formation process comprises
supplying, in a cycle period, silane-based gas and germanium-based gas over the passivation layer, wherein a flow rate ratio between silane-based gas and germanium-based gas is raised and then reduced during the cycle period.

7 . The method of claim 6 ,
wherein the cycle period includes an initial session, an intermediate session and a final session; wherein, in the initial session, the flow rate ratio is set in a range from about 10% to 30%; wherein, in the intermediate session, the flow rate ratio is set in a range from about 30% to 90%; and wherein in the final session, the flow rate ratio is set in a range from about 10% to 30%.

8 . The method of claim 7 ,
wherein a duration length ratio between the intermediate session and the initial session has a range of about 2 to about 3.

9 . The method of claim 8 ,
wherein a duration length ratio between the intermediate session and the final session has a range of about 2 to about 3.

10 . The method of claim 9 , further comprising
performing a plurality of the alloy layer formation process to form a plurality of the SiGe layers stacked over the passivation layer.

11 . The method of claim 10 ,
wherein a thickness of the stacked SiGe layers is in a range from about 1200 to about 1600 Å.

12 . The method of claim 11 ,
wherein a thickness of the middle portion of each of the SiGe layer is in a range from about 100 to about 200 Å.

13 . The method of claim 2 , further comprising
disposing a top conductive layer on the SiGe layer; and disposing a buffer layer formed on the top conductive layer, wherein the lattice constant of the buffer layer is greater than that of the top conductive layer.

14 . The method of claim 13 , wherein
a major metal content in the buffer layer is different from that in the top conductive layer.

15 . The method of claim 1 , further comprising
forming a well region in the substrate; patterning the SiGe layer and the dielectric layer to form a gate feature; and performing a source/drain region formation process to form a source region and a drain region abuts the gate feature.

16 . A method, comprising
receiving a substrate; disposing, over the substrate, a plurality of lower electrodes, wherein each of the lower electrodes has a U-shaped profile in a cross section thereof; disposing a dielectric liner on the lower electrodes; disposing a metallic material filling the U-shaped profile of the lower electrodes, wherein the metallic material has a substantially planar top surface extends across the lower electrodes and fills in and between the U-shaped profile of the lower electrode; disposing a silicon film on the substantially planar top surface of the metallic material; and performing an alloy layer formation process to dispose a SiGe layer across top surface of the silicon film.

17 . The method of claim 16 , wherein the performing the alloy layer formation process comprises
supplying, in a cycle period, silane-based gas and germanium-based gas over the silicon film, wherein a flow rate ratio between silane-based gas and germanium-based gas is raised and then reduced during the cycle period.

18 . A method, comprising
receiving a substrate; disposing, over the substrate, a lower electrode having a U-shaped profile in a cross section thereof; disposing a dielectric liner on the lower electrode; disposing a metallic material filling the U-shaped profile of the lower electrode; disposing a silicon film on top surface of the metallic material; performing an alloy layer formation process to dispose a SiGe layer across top surface of the silicon film; disposing a top conductive layer on the SiGe layer; and disposing a buffer layer formed on the top conductive layer, wherein the lattice constant of the buffer layer is greater than that of the top conductive layer.

19 . The method of claim 18 , wherein
a major metal content in the buffer layer is different from that in the top conductive layer.

20 . The method of claim 18 , wherein
the disposing the buffer layer comprises performing a Physical Vapor Deposition.

Assignees

• Xia Tai Xin Semiconductor Qing Dao Ltd

Inventors

• Choi Keewoung
• Lee Hasung
• Kim Sung-Ki

Classifications

• H10D1/696 Primary

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title

• H10B12/033

  the capacitor extending over the transistor · CPC title

• H10B12/34

  the transistor being at least partially in a trench in the substrate · CPC title