Semiconductor device

Patent metadata

Field	Value
Publication number	US-2020219810-A1
Application number	US-201916550189-A
Country	US
Kind code	A1
Filing date	Aug 24, 2019
Priority date	Jan 8, 2019
Publication date	Jul 9, 2020
Grant date	—

Abstract

A semiconductor device includes a substrate having a first region, a second region, a first buffer region, and a second buffer region. A plurality of conductive lines is disposed on the first region of the substrate. An inductor is disposed on the second region of the substrate, and a dummy pattern is disposed on the first buffer region of the substrate. The first buffer region is provided between the first region and the second region. The second buffer region is provided between the first buffer region and the second region.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate having a first region, a second region, a first buffer region, and a second buffer region; a plurality of conductive lines on the first region of the substrate; an inductor on the second region of the substrate; and a dummy pattern on the first buffer region of the substrate, wherein: the first buffer region is provided between the first region and the second region, and the second buffer region is provided between the first buffer region and the second region.

2 . The semiconductor device of claim 1 , wherein when viewed in plan, a minimum distance between the dummy pattern and the conductive lines is less than a minimum distance between the dummy pattern and the inductor.

3 . The semiconductor device of claim 1 , wherein the dummy pattern is not provided on the second buffer region of the substrate.

4 . The semiconductor device of claim 1 , further comprising:
a plurality of transistors on the first region of the substrate, wherein the conductive lines are electrically connected to the transistors.

5 . The semiconductor device of claim 1 , further comprising:
an interlayer dielectric layer on the substrate and having a first top surface and a second top surface connected to each other, wherein: the conductive lines are disposed on the first top surface of the interlayer dielectric layer, the inductor includes a conductor on the second top surface of the interlayer dielectric layer, and the second top surface of the interlayer dielectric layer is located at a different level from that of the first top surface of the interlayer dielectric layer.

6 . The semiconductor device of claim 5 , wherein top surfaces of the conductive lines are located at a lower level than that of a top surface of the conductor.

7 . The semiconductor device of claim 6 , wherein a level difference between a top surface of the dummy pattern and the top surfaces of the conductive lines is less than a level difference between the top surface of the conductor and the top surface of the dummy pattern.

8 . The semiconductor device of claim 5 , wherein the dummy pattern is not provided on or in the interlayer dielectric layer on the second region of the substrate.

9 . A semiconductor device comprising:
a substrate having a first region, a second region, and a buffer region between the first region and the second region; a lower interlayer dielectric layer on the substrate; a conductive line on a top surface of the lower interlayer dielectric layer on the first region of the substrate; a dummy pattern on the top surface of the lower interlayer dielectric layer on the buffer region of the substrate; and an inductor on the second region of the substrate, wherein: the inductor includes a conductor on the top surface of the lower interlayer dielectric layer, and a top surface of the conductive line is provided at a different level from that of a top surface of the conductor.

10 . The semiconductor device of claim 9 , wherein a level difference between a top surface of the dummy pattern and the top surface of the conductive line is less than a level difference between the top surface of the conductor and the top surface of the dummy pattern.

11 . The semiconductor device of claim 9 , wherein:
the buffer region includes:
a first buffer region between the first region and the second region; and
a second buffer region between the first buffer region and the second region, and
the dummy pattern is provided on the first buffer region of the substrate and is not provided on the second buffer region of the substrate.

12 . The semiconductor device of claim 9 , wherein the top surface of the lower interlayer dielectric layer on the first region of the substrate is provided at a different level from that of the top surface of the lower interlayer dielectric layer on the second region of the substrate.

13 . The semiconductor device of claim 9 , further comprising:
an upper interlayer dielectric layer on the lower interlayer dielectric layer, wherein: the upper interlayer dielectric layer includes:
a first top surface on the first region of the substrate; and
a second top surface on the second region of the substrate and connected to the first top surface, and
the first top surface is provided at a different level from that of the second top surface.

14 . The semiconductor device of claim 13 , wherein
the top surface of the conductive line is coplanar with the first top surface of the upper interlayer dielectric layer, and the top surface of the conductor is coplanar with the second top surface of the upper interlayer dielectric layer.

15 . The semiconductor device of claim 9 , further comprising:
a lower conductive line on the lower interlayer dielectric layer on the first region of the substrate; and a lower dummy pattern in the lower interlayer dielectric layer on the buffer region of the substrate, wherein the inductor is not provided in the lower interlayer dielectric layer.

16 . The semiconductor device of claim 15 , wherein the dummy pattern is not provided on and in the lower interlayer dielectric layer on the second region of the substrate.

17 . A semiconductor device comprising:
a substrate having a first region, a second region, and a buffer region between the first region and the second region; a plurality of internal components on the first region of the substrate; a plurality of conductive lines on the first region of the substrate and electrically connected to the internal components; an inductor on the second region of the substrate; and a dummy pattern on the buffer region of the substrate, wherein when viewed in plan, a minimum distance between the dummy pattern and the conductive lines is less than a minimum distance between the dummy pattern and the inductor.

18 . The semiconductor device of claim 17 , further comprising:
an interlayer dielectric layer on the substrate and having a first top surface and a second top surface connected to each other, wherein: the conductive lines are disposed on the first top surface of the interlayer dielectric layer, the inductor includes a conductor on the second top surface of the interlayer dielectric layer, and the first top surface of the interlayer dielectric layer is provided at a lower level than that of the second top surface.

19 . A semiconductor device having a first region and a second region, which is mutually exclusive with the first region, the semiconductor device comprising:
a substrate; a first dielectric layer disposed over the substrate in each of the first region and the second region; a second dielectric layer disposed over the first dielectric layer in each of the first region and the second region; a first conductor formed within the first dielectric layer and directly electrically connected to a first electronic device; a second conductor formed within the second dielectric layer; and a dummy conductor, formed in the first dielectric layer, that is not electrically connected to an electronic device, wherein: the first conductor and dummy conductor are disposed in the first region, but not in the second region, and the second conductor is disposed in the second region but not the first region.

20 . The semiconductor device of claim 19 , wherein the dummy conductor is disposed between the first conductor and the second conductor, from a perspective of a plan view.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Joon-Nyung
• Ahn Jeong Hoon

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/497 Primary

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/40 Primary

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D84/00 Primary

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• H01L23/528

  Electricity · mapped topic