Method of forming semiconductor structure

Patent metadata

Field	Value
Publication number	US-2020219761-A1
Application number	US-201916679338-A
Country	US
Kind code	A1
Filing date	Nov 11, 2019
Priority date	Dec 24, 2018
Publication date	Jul 9, 2020
Grant date	—

Abstract

A method of forming an oxide structure is disclosed. The method includes forming trenches on a top surface of a substrate and performing a surface treatment process on the substrate. The surface treatment includes forming an amorphous layer on the substrate, removing a portion of the amorphous layer to form a liner layer, and forming a dielectric liner on the liner layer. The liner layer formed are substantially uniform in thickness to prevent contamination and pinhole defects on the oxide structure.

First claim

What is claimed is:

1 . A method of forming an oxide, comprising:
forming a first set of trenches on a top surface of a substrate; and performing a surface treatment on the substrate, the surface treatment process comprising: forming an amorphous layer on the substrate; etching a portion of the amorphous layer to form a liner layer, wherein the amorphous layer is thicker than the liner layer; and disposing a dielectric material on the liner layer.

2 . The method of claim 1 , further comprising:
forming a second set of trenches on a top surface of a substrate.

3 . The method of claim 2 , wherein a distance of a bottom of the first set of trenches from the top surface of the substrate are greater than a distance of a bottom of the second set of trenches from the top surface of the substrate.

4 . The method of claim 2 , wherein the first set of trenches and the second set of trenches are formed simultaneously.

5 . The method of claim 2 , further comprising:
repeating the surface treatment after forming the second set of trenches.

6 . The method of claim 2 , wherein a width of an opening of the first set of trenches is greater than a width of opening of the second set of trenches.

7 . The method of claim 1 , wherein forming the amorphous layer on the substrate is depositing an amorphous material on the top surface of the substrate using chemical vapor deposition.

8 . The method of claim 1 , wherein the first set of trenches does not penetrate through a bottom surface of the substrate.

9 . The method of claim 1 , wherein a thickness of the amorphous layer is at least 100 Å.

10 . The method of claim 1 , wherein a thickness of the liner layer is less than 30 Å.

11 . The method of claim 1 , wherein a thickness of the amorphous layer is about 3 to 5 times a thickness of the liner layer.

12 . The method of claim 1 , wherein etching the portion of the amorphous layer to form the liner layer includes wet etching process using Standard Cleaning 1 (SC1) etchant.

13 . The method of claim 12 , wherein the SC1 etchant includes at least one of NH 4 OH, H 2 O 2 , and di-ionized water.

14 . The method of claim 1 , wherein etching the portion of the amorphous layer to form the liner layer includes wet etching process using hydrofluoric acid (O 3 _HF) etchant.

15 . A method of fabricating a semiconductor device, comprising:
forming a plurality of trenches on a top surface of a substrate; performing a surface treatment process on the substrate, the surface treatment process comprising:
forming an amorphous lining layer on the substrate over exposed surface in the trenches;
reducing a thickness of the amorphous lining layer; and
converting the amorphous layer at least partially into a dielectric lining layer; and
disposing a conductive material over the dielectric lining layer to fill the trench.

16 . A semiconductor structure, comprising:
a substrate having a plurality of trenches; an amorphous liner layer disposed on a top surface of the substrate and within at least one of the plurality of trenches; and a dielectric liner layer disposed on the amorphous liner layer.

17 . The structure of claim 16 , wherein the plurality of trenches having a first set of trenches and a second set of trenches and the amorphous liner layer only disposed in the first set of trenches.

18 . The structure of claim 16 , further comprising a supplementary liner layer disposed between the substrate and the dielectric liner layer.

19 . The structure of claim 16 , wherein a thickness of the amorphous liner layer is about 30 Å.

20 . The structure of claim 16 , wherein the plurality of trenches having substantially same depth from a top surface of the substrate.

Assignees

• Xia Tai Xin Semiconductor Qing Dao Ltd

Inventors

• Choi Jong-Moo
• Park Heung-Woo
• Kim Sung-Ki

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H10P14/6308

  of Group IV semiconductors · CPC title

• H10P14/416

  of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10D64/0135

  by deposition of a layer, e.g. metal, metal compound or polysilicon, followed by transformation thereof into the insulator · CPC title

• H10W10/0142

  the dielectric materials being chemical transformed from non-dielectric materials · CPC title