Array substrate and preparation method therefor, and display panel and display device

Patent metadata

Field	Value
Publication number	US-2020212071-A1
Application number	US-201916640940-A
Country	US
Kind code	A1
Filing date	Mar 22, 2019
Priority date	Apr 9, 2018
Publication date	Jul 2, 2020
Grant date	—

Abstract

The present disclosure relates to the technical field of display. Disclosed are an array substrate and a preparation method therefor, and a display panel and a display device. The array substrate includes: a substrate; multiple gate lines, wherein the gate lines are located on the substrate, and extend along a first direction; multiple data lines, wherein the data lines are located on the substrate, and extend along a second direction, and the gate lines and the data lines intersect to define multiple pixel areas; and a touch-control electrode wiring wherein the touch-control electrode wiring has the same direction as that of the gate lines, and is arranged insulated from the gate lines on a different layer, and the orthographic projection of the touch-control electrode wiring on the substrate at least has an overlapping area with the orthographic projection of part of the gate lines on the substrate.

First claim

1 . An array substrate, comprising:
a substrate; a plurality of gate lines, located on the substrate and extending in a first direction; a plurality of data lines, located on the substrate and extending in a second direction, wherein the gate lines and the data lines intersect to define a plurality of pixel areas; and a plurality of touch-control electrode wirings, extending in the same direction with the gate lines and being insulated from the gate lines on a different layer, wherein an orthographic projection of the touch-control electrode wirings on the substrate at least has an overlapped area with an orthographic projection of a part of the gate lines on the substrate.

2 . The array substrate according to claim 1 , wherein the touch-control electrode wirings are arranged in one-to-one correspondence to the gate lines.

3 . The array substrate according to claim 1 , wherein the touch-control electrode wirings comprise stacked first-layer wirings and second-layer wirings, wherein materials of the first-layer wirings comprise metal materials, and materials of the second-layer wirings comprise conductive protection materials.

4 . The array substrate according to claim 1 , wherein width of the touch-control electrode wirings is smaller than width of the gate lines.

5 . The array substrate according to claim 1 , wherein the array substrate further comprises touch-control electrodes electrically connected to the touch-control electrode wirings.

6 . The array substrate according to claim 5 , wherein the array substrate further comprises an insulating layer located between a touch-control electrode wiring layer and the touch-control electrodes; and
the touch-control electrode wirings are electrically connected to the touch-control electrodes through via holes located in the insulating layer.

7 . The array substrate according to claim 6 , wherein the array substrate further comprises pixel electrodes located in the pixel areas, wherein driving electrical fields are formed between the pixel electrodes and common electrodes.

8 . The array substrate according to claim 7 , wherein the touch-control electrodes are multiplexed as the common electrodes.

9 . A display panel, comprising an array substrate, wherein the array substrate comprises:
a substrate; a plurality of gate lines, located on the substrate and extending in a first direction; a plurality of data lines, located on the substrate and extending in a second direction, wherein the gate lines and the data lines intersect to define a plurality of pixel areas; and a plurality of touch-control electrode wirings, extending in the same direction with the gate lines and being insulated from the gate lines on a different layer, wherein an orthographic projection of the touch-control electrode wirings on the substrate at least has an overlapped area with an orthographic projection of a part of the gate lines on the substrate.

10 . A display device, comprising the display panel according to claim 9 .

11 . A preparation method of an array substrate, comprising:
forming a grid line layer on a substrate, and a plurality of gate lines with a composition process; and forming a plurality of touch-control electrode wirings on the gate lines, wherein an orthographic projection of the touch-control electrode wirings on the substrate at least has an overlapped area with an orthographic projection of a part of the gate lines on the substrate.

12 . The preparation method according to claim 11 , wherein the preparation method further comprises:
forming an insulating layer on the touch-control electrode wirings, and forming via holes in the insulating layer with the composition process; and forming a touch-control electrode layer on the insulating layer in which the via holes are formed, and forming touch-control electrodes with the composition process; wherein the touch-control electrodes are electrically connected to the touch-control electrode wirings through the via holes.

13 . The preparation method according to claim 11 , wherein the forming the touch-control electrode wirings on the gate lines comprises:
forming a first-layer wiring layer on the gate lines, wherein materials of the first-layer wiring layer comprise metal materials; forming a second-layer wiring layer on the first-layer wiring layer, wherein materials of the second-layer wiring layer comprise conductive protection materials; and forming the touch-control electrode wirings with the composition process, wherein the touch-control electrode wirings comprise a double-layer structure including a first-layer wiring and a second-layer wiring.

Assignees

• Ordos Yuansheng Optoelectronics Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Guo Zhixuan
• Wang Fengguo
• Fang Yezhou
• Li Feng
• Wu Xinguo
• Liu Hong
• Wang Zifeng
• Li Lei
• Li Feng
• Li Kai
• Tian Liang
• Zhao Jing
• Wang Zhengkui
• Ma Bo
• Liang Haiqin
• Liu Peng

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D30/6723

  having light shields · CPC title

• H10D86/021

  of multiple TFTs · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10D86/40 Primary

  characterised by multiple TFTs · CPC title