Protection circuit

Patent metadata

Field	Value
Publication number	US-2020210569-A1
Application number	US-201916728946-A
Country	US
Kind code	A1
Filing date	Dec 27, 2019
Priority date	Dec 28, 2018
Publication date	Jul 2, 2020
Grant date	—

Abstract

In an embodiment, an electronic circuit includes a plurality of protective nodes. Each protective node includes at least one monitoring circuit for processing information representative of a detection of a disturbance based on a detection circuit; and at least one reaction circuit for implementing a countermeasure controlled by the monitoring circuit.

First claim

What is claimed is:

1 . An electronic circuit comprising:
a plurality of protective nodes, each protective node of the plurality of protective nodes comprising: a respective monitoring circuit configured to process information representative of a detection of a disturbance generated by a detection circuit; and a respective reaction circuit configured to perform a countermeasure controlled by the respective monitoring circuit.

2 . The electronic circuit of claim 1 , wherein each protective node comprises the detection circuit coupled to the respective monitoring circuit, wherein the detection circuit is configured to detect a disturbance.

3 . The electronic circuit of claim 2 , wherein each monitoring circuit of the electronic circuit is configured to receive information from all detection circuits of the electronic circuit.

4 . The electronic circuit according to claim 1 , wherein each monitoring circuit of the electronic circuit is configured to communicate to each other of the monitoring circuits of the electronic circuit.

5 . The electronic circuit according to claim 4 , wherein each monitoring circuit of the electronic circuit is coupled to a bus, and wherein each monitoring circuit of the electronic circuit is configured to communicate to each other of the monitoring circuits of the electronic circuit via the bus.

6 . The electronic circuit according to claim 4 , wherein each monitoring circuit of the electronic circuit is coupled to each other of the monitoring circuits of the electronic circuit via respective dedicated links, and wherein each monitoring circuit of the electronic circuit is configured to communicate to each other of the monitoring circuits of the electronic circuit via the respective dedicated links.

7 . The electronic circuit of claim 1 , wherein a protective node of the plurality of protective nodes comprises a plurality of detection circuits coupled to the respective monitoring circuit, each detection circuit of the plurality of detection circuits configured to detect disturbances.

8 . The electronic circuit of claim 1 , wherein a protective node of the plurality of protective nodes comprises a plurality of reaction circuits coupled to the respective monitoring circuit, each reaction circuit of the plurality of reaction circuits configured to perform countermeasures controlled by the respective monitoring circuit.

9 . The electronic circuit of claim 1 , wherein the electronic circuit is a microcontroller.

10 . The electronic circuit of claim 1 , further comprising a reset circuit configured to reset the electronic circuit based on a reaction circuit of a protective node of the plurality of protective nodes.

11 . A method comprising:
detecting a disturbance in an electronic circuit with a first detection circuit of a first protective node of a plurality of protective nodes of the electronic circuit; processing information representative of the detected disturbance with a first monitoring circuit of the first protective node; and performing a first countermeasure with a first reaction circuit of the first protective node based on an output of the first monitoring circuit.

12 . The method of claim 11 , further comprising:
receiving, by a second monitoring circuit of a second protective node of the plurality of protective nodes, information representative of the detected disturbance from the first monitoring circuit; and performing a second countermeasure with a second reaction circuit of the second protective node based on an output of the second monitoring circuit.

13 . The method of claim 12 , wherein the first countermeasure is different from the second countermeasure.

14 . The method of claim 12 , wherein the first protective node is associated with a first circuit, wherein the second protective node is associated with a second circuit, wherein the first countermeasure comprises modifying an aspect of the first circuit, and wherein the second countermeasure comprises modifying an aspect of the second circuit.

15 . The method of claim 14 , wherein the first circuit is a memory, and wherein modifying an aspect of the first circuit comprises blocking writing into the memory, blocking access into the memory, deleting content of the memory.

16 . The method of claim 12 , further comprising transmitting the information representative of the detected disturbance from the first monitoring circuit to the second monitoring circuit via a bus that is coupled to all protective nodes of the plurality of protective nodes.

17 . The method of claim 12 , further comprising transmitting the information representative of the detected disturbance from the first monitoring circuit to the second monitoring circuit via a dedicated link that is coupled between the first monitoring circuit and the second monitoring circuit.

18 . The method of claim 11 , wherein the disturbance is caused by an attack.

19 . The method of claim 18 , wherein the attack comprises a focused ion beam (FIB) attack, or physically cutting off or diverting an electrical path of the electronic circuit.

20 . A microcontroller comprising:
a first protective node comprising:
a first detection circuit configured to detect a disturbance of the microcontroller,
a first monitoring circuit configured to process information representative of the detected disturbance, and
a reaction circuit configured to perform a first countermeasure based on an output of the first monitoring circuit; and
a second protective node comprising:
a second monitoring circuit configured receive information representative of the detected disturbance from the first monitoring circuit, and
a second reaction circuit configured to perform a second countermeasure based on an output of the second monitoring circuit.

21 . The microcontroller of claim 20 , further comprising:
a first circuit associated with the first protective node; and a second circuit associated with the second protective node, wherein the first countermeasure comprises modifying an aspect of the first circuit, and wherein the second countermeasure comprises modifying an aspect of the second circuit.

Assignees

• St Microelectronics Rousset
• St Microelectronics Alps Sas

Inventors

• Moisuc Diana
• Laurencin Christophe

Classifications

• H10W42/405

  using active circuits · CPC title

• G06F1/24

  Resetting means · CPC title

• G06F21/554 Primary

  involving event detection and direct action · CPC title

• H02H1/0007

  concerning the detecting means (in general G01R or other subclasses of G01; reed switches H01H71/2445) · CPC title

• G06F2221/034

  Test or assess a computer or a system · CPC title