Solid-state electronic scanning laser array with high-side and low-side switches for increased channels

US2020209355A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2020209355-A1
Application numberUS-201916696540-A
CountryUS
Kind codeA1
Filing dateNov 26, 2019
Priority dateDec 26, 2018
Publication dateJul 2, 2020
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

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An electronically scanning emitter array that includes a two-dimensional array of light emitters arranged in k emitter banks. Each of the k emitter banks can include a subset of the light emitters in the two-dimensional array and can be independently operable to emit light from its subset of emitters. The electronically scanning emitter array can further include first and second capacitor banks coupled to provide energy to the two-dimensional array of light emitters and emitter array driving circuitry coupled to the first and second capacitor banks and to the k emitter banks. Each of the first and second capacitor banks can include at least one capacitor. The emitter array driving circuitry can include a first high-side switch coupled between the first capacitor bank and a voltage source, a second high-side switch coupled between the second capacitor bank and the voltage source, and k/2 low-side switches coupled between the k emitter banks and ground; and the emitter driving circuitry can be configured to fire one emitter bank in the k emitter banks at a time according to a firing sequence until each of the k emitter banks are fired.

First claim

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What is claimed is: 1 . An electronically scanning emitter array comprising: a two-dimensional array of light emitters comprising k emitter banks, wherein each of the k emitter banks includes a subset of emitters in the two-dimensional array of light emitters and is independently operable to emit light from its subset of emitters; and first and second capacitor banks coupled to provide energy to the two-dimensional array of light emitters, each of the first and second capacitor banks including at least one capacitor; and emitter array driving circuitry coupled to the first and second capacitor banks and to the k emitter banks, the emitter array driving circuitry configured to fire one emitter bank in the k emitter banks at a time according to a firing sequence until each of the k emitter banks are fired, the emitter array driving circuitry including a first high-side switch coupled between the first capacitor bank and a voltage source, a second high-side switch coupled between the second capacitor bank and the voltage source, and k/2 low-side switches coupled between the k emitter banks and ground. 2 . The electronically scanning emitter array of claim 1 wherein the two-dimensional array of light emitters is aligned to project discrete beams of light into a field external to the emitter array according to an illumination pattern in which each discrete beam in the illumination pattern represents a non-overlapping field-of-view within the field. 3 . The electronically scanning emitter array of claim 2 wherein the k emitter banks aligned side-by-side within the two-dimensional array of emitters. 4 . The electronically scanning emitter array of claim 1 wherein: the k emitter banks comprises a first plurality of emitter banks and a second plurality of emitter banks; the first capacitor bank is coupled to the anodes of the first plurality of emitter banks; the second capacitor bank is coupled to the anodes of the second plurality of emitter banks; and the emitter array driving circuitry is configured to drive the emitter array in a plurality of consecutive emission cycles in which, during each emission cycle, the firing sequence fires all of the first plurality of emitter banks and then fires all of the second plurality of emitter banks. 5 . The electronically scanning emitter array of claim 4 wherein each of the first and second pluralities of emitter banks includes n emitter banks, and during each emission cycle, the emitter array driving circuitry is configured to: partially discharge the first capacitor bank after firing each of the first to the nth emitter banks in the first plurality of emitter banks and then, after firing all of the emitter banks in the first plurality of emitter banks, fully discharge the first capacitor bank; and partially discharge the second capacitor bank after firing each of the first to the nth emitter banks in the second plurality of emitter banks and then, after firing all of the emitter banks in the second plurality of emitter banks, fully discharge the second capacitor bank. 6 . The electronically scanning emitter array of claim 1 wherein the k emitter banks comprises a first plurality of emitter banks and a second plurality of emitter banks; the first capacitor bank is coupled to the anodes of the first plurality of emitter banks; the second capacitor bank is coupled to the anodes of the second plurality of emitter banks; and the emitter array driving circuitry is configured to drive the emitter array in a plurality of consecutive emission cycles in which, during each emission cycle, the firing sequence alternates between firing an emitter bank from the first plurality of emitter banks and an emitter bank from the second plurality of emitter banks. 7 . The electronically scanning emitter array of claim 6 wherein the emitter array driving circuitry is configured to, after each instance of firing an emitter bank, fully discharge the capacitor bank coupled to the emitter. 8 . The electronically scanning emitter array of claim 1 wherein each of the low-side switches is configured to handle at least 10 times an amount of current as the first and second high-side switches. 9 . The electronically scanning emitter array of claim 1 further comprising a diodes coupled in series with each emitter bank between the emitter bank and its respective low-side switch, the diode configured to withstand high reverse voltages to protect the emitter bank from undesirable current flow through the emitter bank. 10 . The electronically scanning emitter array of claim 1 further comprising a gate driver coupled to each low-side switch, the gate driver configured to turn ON its respective low-side switch in response to a control signal. 11 . The electronically scanning emitter array of claim 1 wherein each emitter in the plurality of emitters comprises a vertical cavity surface emitting laser (VCSEL). 12 . An electronically scanning emitter array comprising: a two-dimensional array of light emitters comprising k emitter banks, wherein each of the k emitter banks includes a subset of emitters in the two-dimensional array of light emitters and is independently operable to emit light from its subset of emitters; and a plurality of capacitors arranged as l capacitor banks and coupled to provide energy to the two-dimensional array of light emitters, each of the l capacitor banks including at least one capacitor; emitter array driving circuitry coupled to the l capacitor banks and to the k emitter banks, the emitter array driving circuitry configured to fire one emitter bank in the k emitter banks at a time according to a firing sequence until each of the k emitter banks are fired, the emitter array driving circuitry including: l high-side switches, each of the l high-side switches coupled between one of the l capacitor banks and a voltage source; and k/l low-side switches, each of the k/l low-side switches coupled between one the k emitter banks and ground. 13 . A solid state optical system comprising: a two-dimensional array of light emitters comprising k emitter banks, wherein each of the k emitter banks includes a subset of emitters in the two-dimensional array of light emitters and is independently operable to emit light from its subset of emitters; an array of photosensors comprising k photosensor banks, wherein each of the k photosensor banks is paired with one of the k emitter banks in the light transmission module; first and second capacitor banks coupled to provide energy to the two-dimensional array of light emitters, each of the first and second capacitor banks including at least one capacitor; and emitter array driving circuitry coupled to the first and second capacitor banks and to the k emitter banks, the emitter array driving circuitry configured to fire one emitter bank in the k emitter banks at a time according to a firing sequence until each of the k emitter banks are fired, the emitter array driving circuitry including a first high-side switch coupled between the first capacitor bank and a voltage source, a second high-side switch coupled between the second capacitor bank and the voltage source, and k/2 low-side switches coupled between the k emitter banks and ground; and sensor array readout circuity coupled to the array of photosensors and configured to synchronize the readout of each of the k photosensor banks within the array concurrently with the firing of its corresponding emitter bank in the k emitter banks so that each light emitter in the two-dimensional array of individual light emitters can be activated and each photosensor in the array of photosensors can be readout through one emiss

Assignees

Inventors

Classifications

  • using multiple transmitters · CPC title

  • using transmission of interrupted, pulse-modulated waves (determination of distance by phase measurements G01S17/32) · CPC title

  • G01S7/484Primary

    Transmitters · CPC title

  • G01S7/4817Primary

    relating to scanning · CPC title

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What does patent US2020209355A1 cover?
An electronically scanning emitter array that includes a two-dimensional array of light emitters arranged in k emitter banks. Each of the k emitter banks can include a subset of the light emitters in the two-dimensional array and can be independently operable to emit light from its subset of emitters. The electronically scanning emitter array can further include first and second capacitor banks…
Who is the assignee on this patent?
Ouster Inc
What technology area does this patent fall under?
Primary CPC classification G01S7/484. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Jul 02 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).