Capacitor and board having the same

Patent metadata

Field	Value
Publication number	US-2020205291-A1
Application number	US-202016804381-A
Country	US
Kind code	A1
Filing date	Feb 28, 2020
Priority date	Jul 20, 2016
Publication date	Jun 25, 2020
Grant date	—

Abstract

A capacitor includes a body including a plurality of dielectric layers, first and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween, and first and second insulating regions. The first insulating region is disposed in each of the first internal electrodes and includes a first connection electrode disposed therein. The second insulating region is disposed in each of the second internal electrodes and includes a second connection electrode disposed therein. The products D1×Td and D2×Td are greater than 20 μm 2 , where Td is a thickness of the dielectric layer, and D1 and D2 are widths of the first and second insulating regions, respectively.

First claim

What is claimed is:

1 . A capacitor comprising:
a body including a plurality of dielectric layers; first and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween; a first insulating region, disposed in each of the first internal electrodes, including a first connection electrode disposed therein; and a second insulating region, disposed in each of the second internal electrodes, including a second connection electrode disposed therein, wherein D 1 ×Td and D 2 ×Td are greater than 20 μm 2 and 60 μm 2 or less, where Td is a thickness of the dielectric layer, and D 1 and D 2 are widths of the first and second insulating regions, respectively.

2 . The capacitor of claim 1 , wherein the first and second insulating regions and the first and second connection electrodes are disposed at edges of the first and second internal electrodes.

3 . The capacitor of claim 1 , wherein the capacitor includes at least two first insulating regions each disposed in each of the first internal electrodes, at least two second insulating regions disposed in each of the second internal electrodes, at least two first connection electrodes disposed in the at least two first insulating regions and interconnecting the second internal electrodes, and at least two second connection electrodes disposed in the at least two second insulating regions and interconnecting the first internal electrodes.

4 . The capacitor of claim 1 , further comprising first and second external electrodes disposed on an external surface of the body,
wherein the first external electrode is electrically connected to the first internal electrodes through the second connection electrode, and the second external electrode is electrically connected to the second internal electrodes through the first connection electrode.

5 . The capacitor of claim 1 , wherein a distance between the first and second connection electrodes is equal to or less than 85% of a length of the body.

6 . The capacitor of claim 1 , wherein at least portions of the first and second internal electrodes are exposed to a side surface of the body.

7 . A board having a capacitor, the board comprising:
a circuit board having an upper surface on which first and second electrode pads are formed; and the capacitor of claim 1 , mounted on the first and second electrode pads of the circuit board.

8 . A capacitor comprising:
a body including a plurality of dielectric layers; first and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween; a first insulating region, disposed in each of the first internal electrodes, including a first connection electrode disposed therein; and a second insulating region, disposed in each of the second internal electrodes, including a second connection electrode disposed therein; wherein D 1 ×Td and D 2 ×Td are greater than 20 μm 2 and 60 μm 2 or less, where Td is a thickness of the dielectric layer, and D 1 and D 2 are widths of the first and second insulating regions, respectively.

9 . The capacitor of claim 8 , wherein D 1 is a minimum distance between a first internal electrode and the first connection electrode, and D 2 is a minimum distance between a second internal electrode and the second connection electrode.

10 . The capacitor of claim 8 , wherein the first connection electrode interconnects the second internal electrodes and is insulated from the first internal electrodes by the first insulating region, and the second connection electrode interconnects the first internal electrodes and is insulated from the second internal electrodes by the second insulating region.

11 . The capacitor of claim 8 , wherein the first insulating region contacts an edge of the first internal electrodes, and the second insulating region contacts an edge of the second internal electrodes.

12 . The capacitor of claim 11 , wherein the first insulating region has a substantially semi-circular shape surrounding the first connection electrode, and
the second insulating region has a substantially semi-circular shape surrounding the second connection electrode.

13 . The capacitor of claim 8 , wherein a distance between the first and second connection electrodes is greater than a sum of radii of the first and second connection electrodes, the widths D 1 and D 2 of the first and second insulating regions, and a 20 μm interval.

Assignees

• Samsung Electro Mech

Inventors

• Jung Jin Man
• Joo Jin Kyung
• Chang Ik Hwan
• Lee Taek Jung
• Lee Won Young
• Seo Yong Won
• Chun Jin Woo

Classifications

• Y02P70/50

  Manufacturing or production processes characterised by the final manufactured product · CPC title

• H01G4/12

  Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

• H05K1/181 Primary

  associated with surface mounted components · CPC title

• H05K3/3431

  Leadless components · CPC title

• H05K2201/10015

  Non-printed capacitor · CPC title