Array substrate, method for fabricating the same and display panel

Patent metadata

Field	Value
Publication number	US-2020203384-A1
Application number	US-201916388736-A
Country	US
Kind code	A1
Filing date	Apr 18, 2019
Priority date	Dec 25, 2018
Publication date	Jun 25, 2020
Grant date	—

Abstract

An array substrate, a method for fabricating the array substrate and a display panel. The array substrate is provided with at least one isolation mesa in each of multiple pixel grooves in a pixel-defining layer, so that a light-emitting layer of a second sub-pixel located on the isolation mesa and a light-emitting layer of a first sub-pixel located on an exposed portion of a bottom surface of the pixel groove are on different planes and thereby isolated. It is prevented that an adjacent sub-pixel is influenced via the light-emitting layer, in a case that the anode of the second sub-pixel and the anode of the first sub-pixel receive different voltages. The isolation mesa does not form a non-emitting region in the pixel groove. An aperture ratio of the array substrate is not reduced. High PPI of the array substrate is ensured.

First claim

1 . An array substrate, comprising:
a first substrate; a pixel-defining layer located on the first substrate, wherein the pixel-defining layer comprises a plurality of pixel grooves arranged in a first array; at least one isolation mesa located in each of the plurality of pixel grooves, wherein a bottom surface of each of the plurality of pixel grooves is partially covered by the at least one isolation mesa; a first sub-pixel located on an uncovered portion of the bottom surface of each of the plurality of pixel grooves; and a second sub-pixel located at a side of the at least one isolation mesa facing away from the first substrate; wherein the first sub-pixel comprises a first anode, the second sub-pixel comprises a second anode, a light-emitting layer is located on the first anode and the second anode, and a cathode located at a side of the light-emitting layer facing away from the first substrate.

2 . The array substrate according to claim 1 , wherein:
one of the at least one isolation mesa comprises a first surface facing the first substrate, and a second surface facing away from the first substrate; and an orthographic projection of the first surface on the first substrate is covered by the orthographic projection of the second surface on the first substrate.

3 . The array substrate according to claim 2 , wherein:
a shape of a cross section perpendicular to the first substrate of the one of the at least one isolation mesa is a trapezoid, a first side of the trapezoid is parallel to a second side of the trapezoid, the second side is located at a side of the first side away from the substrate, and a length of the second side is greater than a length of the first side; or a shape of a cross section of the one of the at least one isolation mesa is a rectangle.

4 . The array substrate according to claim 1 , wherein in each of the plurality of pixel grooves, a quantity of the second sub-pixels is one, a quantity of the first sub-pixels is two, and the two first sub-pixels are respectively located on two sides of the at least one isolation mesa.

5 . The array substrate according to claim 1 , wherein in each of the plurality of pixel grooves, a quantity of the at least one isolation mesas is three; a quantity of the second sub-pixel is three, and a number of the first sub-pixel is three.

6 . The array substrate according to claim 5 , wherein:
the bottom surface of each of the plurality of pixel grooves is a regular hexagon; a top surface of each of the three isolation mesas is an equilateral triangle; and the three isolation mesas share a same vertex, and every two adjacent ones of the at least one isolation mesas is separated by an angle of 60°.

7 . The array substrate according to claim 1 , wherein the at least one isolation mesa comprises one of an organic insulating material and an inorganic insulating material.

8 . The array substrate according to claim 1 , further comprising a pixel-driving film layer and a planarization layer that are located between the first substrate and the pixel-defining layer, wherein:
the planarization layer is located between the pixel-driving film layer and the pixel-defining layer, the planarization layer comprises a plurality of first through holes running through the planarization layer, and the anode is electrically connected to the pixel-driving film layer via the plurality of first through holes.

9 . The array substrate according to claim 8 , wherein the pixel-driving film layer comprises:
a plurality of gate electrodes, arranged in a second array and located on the first substrate; a gate insulating layer, disposed on the plurality of gate electrodes; a plurality of active layers, arranged in a third array and located on a side of the gate insulating layer facing away from the first substrate, wherein each of the plurality of active layers comprises a trench region, a source region and a drain region, and the source region and the drain region are located on two sides of the trench region; a passivation layer, covering the plurality of active layers, wherein the passivation layer comprises a plurality of second through-holes, and each of the source region and the drain region is at least partially exposed by the plurality of second through-holes; and a plurality of source electrodes and a plurality of drain electrodes, located on the passivation layer, wherein the plurality of source electrodes is connected to the source regions of the plurality of active layers via the plurality of second through-holes, the plurality of drain electrodes are connected to the drain regions of the plurality of active layers via the plurality of second through-holes; wherein the anode is electrically connected to one of the plurality of drain electrodes via one of the plurality of first through-holes.

10 . A method for fabricating an array substrate, comprising:
providing a first substrate; forming a pixel-defining layer on the first substrate, wherein the pixel-defining layer comprises a plurality of pixel grooves arranged in a first array; forming, by using a first mask, a first anode of a first sub-pixel in each of the plurality of pixel grooves, wherein a bottom surface of each of the plurality of pixel grooves is partially covered by the first anode of the first sub-pixel; forming, by using a second mask, an isolation mesa in each of the plurality of pixel grooves, wherein the isolation mesa is disposed on the uncovered portion of the bottom surface of each of the plurality of pixel grooves is covered by the isolation mesa; forming, by using the second mask, a second anode of a second sub-pixel on a side of the isolation mesa facing away from the first substrate; providing a third mask on the pixel-defining layer, wherein the first anode of the first sub-pixel and the second anode of the second sub-pixel are exposed by the third mask; forming, by using the third mask, a light-emitting layer on a side of the first anode of the first sub-pixel and the second anode of the second sub-pixel facing away from the first substrate; and forming a cathode on a side of the light-emitting layer facing away from the first substrate, to form the first sub-pixel and the second sub-pixel that is located on a surface of the isolation mesa, wherein a quantity of the first sub-pixel and a quantity of the second sub-pixel are both more than one.

11 . The method according to claim 10 , wherein forming, by using the second mask, the isolation mesa in each of the plurality of pixel grooves comprises:
forming an inorganic insulating material layer that covers at least the plurality of pixel grooves; applying the second mask on the inorganic insulating material layer; and etching, via an etching process using the second mask, the inorganic insulating material layer to form the isolation mesa, wherein a perpendicular cross section of the isolation mesa is a trapezoid, the trapezoid has a first side and a second side that are parallel, the second side is located on a side of the first side away from the substrate, and a length of the second side is greater than a length of the first side.

12 . The method according to claim 10 , wherein forming, by using the second mask, the isolation mesa in each of the plurality of pixel grooves comprises:
forming an organic insulating material layer that covers at least the plurality of pixel grooves, wherein the organic insulating material layer is a negative photoresist organic insulating material layer; and exposing and developing, by using the second mask, the organic insulating material layer to form the isolation mesa, wherein a shape of a perpendicular cross section of the isolation mesa is a

Assignees

• Wuhan Tianma Micro Electronics Co Ltd

Inventors

• Huo Sitao

Classifications

• H10K71/00

  Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

• H10K59/80515

  characterised by their shape · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10K59/122 Primary

  Pixel-defining structures or layers, e.g. banks · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title