GaN HEMT DEVICE STRUCTURE AND METHOD OF FABRICATION

Patent metadata

Field	Value
Publication number	US-2020185508-A1
Application number	US-201816212755-A
Country	US
Kind code	A1
Filing date	Dec 7, 2018
Priority date	Dec 7, 2018
Publication date	Jun 11, 2020
Grant date	—

Abstract

GaN HEMT device structures and methods of fabrication are provided. A masking layer forms a p-dopant diffusion barrier and selective growth of p-GaN in the gate region, using low temperature processing, reduces deleterious effects of out-diffusion of p-dopant into the 2DEG channel. A structured AlxGa1-xN barrier layer includes a first thickness having a first Al %, and a second thickness having a second Al %, greater than the first Al %. At least part of the second thickness of the AlxGa1-xN barrier layer in the gate region is removed, before selective growth of p-GaN in the gate region. The first Al % and first thickness are selected to determine the threshold voltage Vth and the second Al % and second thickness are selected to determine the Rdson and dynamic Rdson of the GaN HEMT, so that each may be separately determined to improve device performance, and provide a smaller input FOM (Figure of Merit).

First claim

1 . A method of fabrication of a GaN HEMT device structure comprising:
providing a substrate; growing an epitaxial layer stack on the substrate, the epitaxial layer stack comprising a buffer layer and a GaN heterostructure comprising a GaN channel layer and an overlying Al x Ga 1-x N barrier layer to form a 2DEG channel region; providing a masking layer over the epitaxial layer stack and patterning the masking layer to define a gate opening exposing a gate region of the Al x Ga 1-x N barrier layer; selectively providing p-GaN on the gate region; defining openings through the masking layer to source and drain regions and providing source and drain electrodes thereon, and providing a gate electrode on the p-GaN gate region.

2 . The method of claim 1 , wherein providing the masking layer comprises deposition of a dielectric passivation layer, the dielectric passivation layer having a thickness and composition that forms a p-dopant diffusion barrier.

3 . The method of claim 2 , wherein selectively providing p-GaN on the gate region comprises selective growth of p-GaN on the gate region, using a low temperature growth process at a temperature below 950 C.

4 . The method of claim 2 , wherein selectively providing p-GaN on the gate region comprises a low temperature growth process at a temperature below 950 C, wherein a p-GaN layer is grown on the gate region and forms polycrystalline p-GaN over the masking layer, and portions of the polycrystalline p-GaN extending over the masking layer are removed leaving a p-GaN mesa on the gate region.

5 . The method of claim 2 , wherein the dielectric passivation layer comprises at least one of a layer of a dielectric oxide and a layer of a dielectric nitride.

6 . The method of claim 2 , wherein the dielectric passivation layer comprises at least one of a layer of dielectric oxide and a layer of dielectric nitride, and wherein patterning the masking layer comprises etching said gate opening to expose the gate region of the Al x Ga 1-x N barrier layer and further etching the Al x Ga 1-x N barrier layer within the gate opening to thin the Al x Ga 1-x N barrier layer in the gate region, before selective area growth of p-GaN on the gate region.

7 . The method of claim 6 , wherein the selective area growth of p-GaN comprises low temperature growth of p-GaN carried out at a temperature below 950 C.

8 . The method of claim 7 , wherein patterning the masking layer to expose the gate region of the Al x Ga 1-x N barrier layer provides a gate opening shape that facilitates selective area growth of p-GaN in the gate opening to reduce any gap within the gate opening between the p-GaN in the gate opening and the masking layer.

9 . The method of claim 8 , further comprising a step of cleaning an exposed surface of the Al x Ga 1-x N barrier layer in the gate opening before selective growth of p-GaN on the gate region.

10 . A GaN HEMT device structure, comprising:
a substrate; an epitaxial layer stack grown on the substrate, the epitaxial layer stack comprising a buffer layer and a GaN heterostructure comprising a GaN layer and an overlying Al x Ga 1-x N barrier layer to form a 2DEG channel region; a passivation layer formed on the Al x Ga 1-x N barrier layer having a gate opening defined on a gate region of the Al x Ga 1-x N barrier layer, and source and drain openings defined on source and drain regions of the Al x Ga 1-x N barrier layer; a mesa of p-doped GaN on the gate region; source and drain electrodes formed on the source and drain regions and a gate electrode formed on the p-doped GaN mesa; and wherein the Al x Ga 1-x N barrier layer comprises a first thickness in the gate region and a second thickness in access regions extending between the gate region and the source region and between the gate region and the drain region; and the first thickness providing a specified threshold voltage and the second thickness providing a specified Rdson of the GaN HEMT device structure.

11 . The GaN HEMT device structure of claim 10 , wherein the passivation layer comprises at least a first layer of a dielectric material that forms a p-dopant diffusion barrier.

12 . The GaN HEMT device structure of claim 11 , wherein said first layer of the dielectric material comprises at least one of a layer of dielectric oxide and a layer of a dielectric nitride.

13 . The GaN HEMT device structure of claim 12 , wherein the p-dopant is magnesium (Mg) and said first layer of dielectric material is a Mg diffusion barrier.

14 . The GaN HEMT device structure of claim 13 , wherein an out-diffused p-dopant content in the access regions of the Al x Ga 1-x N barrier layer is less than an out-diffused p-dopant content in the gate region of the Al x Ga 1-x N barrier layer.

15 . A method of fabrication of a GaN HEMT device structure comprising:
providing a substrate; growing an epitaxial layer stack on the substrate, the epitaxial layer stack comprising a buffer layer and a GaN heterostructure comprising a GaN channel layer and an overlying Al x Ga 1-x N barrier layer to form a 2DEG channel region, wherein the Al x Ga 1-x N barrier layer comprises a first thickness having a first Al %, and a second thickness having a second Al %, greater than the first Al %; providing a masking layer over the epitaxial layer stack and patterning the masking layer to form an opening exposing a gate region of the Al x Ga 1-x N barrier layer; selectively removing at least part of the second thickness of the Al x Ga 1-x N barrier layer within the opening; selectively providing p-GaN on the Al x Ga 1-x N barrier layer within the opening to form a p-GaN gate region; defining openings through the masking layer to source and drain regions and providing source and drain electrodes thereon, and defining a gate electrode on the p-GaN gate region.

16 . The method of claim 15 , comprising selecting the first Al % and the first thickness of the Al x Ga 1-x N barrier layer to provide a specified threshold voltage for E-mode operation, and the second Al % and the second thickness of the Al x Ga 1-x N barrier layer are selected to provide a specified Rdson and dynamic Rdson of the GaN HEMT.

17 . The method of claim 16 , wherein the first Al % is in the range from 15% to 18% and the first thickness of the Al x Ga 1-x N barrier layer in the range 15 nm to 20 nm to define a specified threshold voltage for E-mode operation, and the second Al % is in the range from 20% to 25% and the second thickness of the Al x Ga 1-x N barrier layer is in the range from 5 nm to 10 nm to provide a specified Rdson and dynamic Rdson of the GaN HEMT.

18 . The method of claim 17 , the first Al % and the first thickness of the Al x Ga 1-x N barrier layer provides a specified threshold voltage for E-mode operation of at least 1.3V.

19 . The method of claim 18 , where providing a masking layer comprises providing a passivation layer comprising at least a first layer of a dielectric material that forms a p-dopant diffusion barrier, and wherein selectively providing p-GaN on the gate region comprises selective growth of p-GaN on the gate region, using a low temperature growth process at a temperature below 950 C.

20 . A GaN HEMT device structure comprising:
a substrate; an epitaxial layer stack grown on the substrate, the epitaxial layer stack comprising a buffer layer and a GaN heterostructure comprising a GaN layer and an overlying Al x Ga 1-x N barrier layer to form a 2DEG channel region; a passivation layer formed on the Al x Ga 1-x N barrier layer having

Assignees

• Gan Systems Inc

Inventors

• Macelwee Thomas

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P14/3456

  Polycrystalline · CPC title

• H10P14/3444

  P-type · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title