Solid-state imaging device and electronic apparatus

Patent metadata

Field	Value
Publication number	US-2020177832-A1
Application number	US-202016783341-A
Country	US
Kind code	A1
Filing date	Feb 6, 2020
Priority date	Jan 28, 2010
Publication date	Jun 4, 2020
Grant date	—

Abstract

A solid-state imaging device includes a pixel region in which shared pixels which share pixel transistors in a plurality of photoelectric conversion portions are two-dimensionally arranged. The shared pixel transistors are divisionally arranged in a column direction of the shared pixels, the pixel transistors shared between neighboring shared pixels are arranged so as to be horizontally reversed or/and vertically crossed, and connection wirings connected to a floating diffusion portion, a source of a reset transistor and a gate of an amplification transistor in the shared pixels are arranged along the column direction.

First claim

What is claimed is:

1 . A light detecting device comprising:
a first unit including:
a first floating diffusion, and
a first reset transistor coupled to the first floating diffusion; and
a second unit disposed adjacent to the first unit in a row direction, the second unit including:
a second floating diffusion, and
a second reset transistor coupled to the second floating diffusion, wherein
a first transistor, a second transistor coupled to the first floating diffusion, a third transistor, and a fourth transistor are adjacent to one another in a first line in this order, and a size of a gate terminal of the first transistor is different from a size of a gate terminal of the second transistor.

2 . The light detecting device of claim 1 , wherein
the size of the gate terminal of the first transistor is smaller than the size of the gate terminal of the second transistor.

3 . The light detecting device of claim 1 , wherein
the size of the gate terminal of the first transistor is the same as a size of a gate terminal of the fourth transistor, and the size of the gate terminal of the second transistor is the same as a size of a gate terminal of the third transistor.

4 . The light detecting device of claim 1 , wherein
a second line is perpendicular to the first line and is disposed between the second transistor and the third transistor, and a first distance between the gate terminal of the first transistor and the second line is the same as a second distance between a gate of the fourth transistor and the second line.

5 . The light detecting device of claim 4 , wherein
a third distance between the gate terminal of the second transistor and the second line is the same as a fourth distance between a gate of the third transistor and the second line.

6 . The light detecting device of claim 1 , wherein
a first set of gate terminals and a second set of gate terminals are symmetrically arranged in the first line, the first set of gate terminals includes the gate terminal of the first transistor and the gate terminal of the second transistor, and the second set of gate terminals includes a gate terminal of the third transistor and a gate terminal of the fourth transistor.

7 . The light detecting device of claim 1 , wherein
a drain region of the second transistor and a drain region of the third transistor are formed of a common diffusion region.

8 . The light detecting device of claim 1 , wherein
the second transistor and the third transistor include a common diffusion region.

9 . The light detecting device of claim 8 , wherein
the common diffusion region is a drain region of the second transistor and a drain region of the third transistor.

10 . A light detecting device comprising:
a first floating diffusion; a first transfer transistor coupled to the first floating diffusion; a second floating diffusion; a second transfer transistor coupled to the second floating diffusion; a first transistor region disposed in a first line, the first transistor region including:
a first transistor,
a second transistor coupled to the first floating diffusion,
a third transistor, and
a fourth transistor; and
a second transistor region disposed in a second line parallel to the first line, the second transistor region including:
a fifth transistor,
a sixth transistor coupled to the second floating diffusion,
a seventh transistor, and
an eighth transistor,
wherein the first floating diffusion, the first transfer transistor, the second floating diffusion, and the second transfer transistor are disposed between the first line and the second line.

11 . The light detecting device of claim 10 , wherein
a size of a gate terminal of the first transistor is different from a size of a gate terminal of the second transistor, and a size of a gate terminal of the fifth transistor is different from a size of a gate terminal of the sixth transistor.

12 . The light detecting device of claim 10 , wherein
a size of a gate terminal of the second transistor is the same as a size of a gate terminal of the sixth transistor, and a size of a gate terminal of the first transistor is different from a size of a gate terminal of the fifth transistor.

13 . The light detecting device of claim 10 , wherein
a drain region of the second transistor and a drain region of the third transistor are formed of a first common diffusion region, and a drain region of the sixth transistor and a drain region of the seventh transistor are formed of a second common diffusion region.

Assignees

• Sony Corp

Inventors

• Kido Hideo
• Yamamoto Atsuhiko
• Yamada Akihiro

Classifications

• H04N25/767 Primary

  Horizontal readout lines, multiplexers or registers · CPC title

• H01L27/14612

  Electricity · mapped topic

• H01L27/14636

  Electricity · mapped topic

• H04N5/3745

  Electricity · mapped topic

• H01L27/148

  Electricity · mapped topic