A power semiconductor device with an auxiliary gate structure

Patent metadata

Field	Value
Publication number	US-2020168599-A1
Application number	US-201816630321-A
Country	US
Kind code	A1
Filing date	Jul 13, 2018
Priority date	Jul 14, 2017
Publication date	May 28, 2020
Grant date	—

Abstract

The disclosure relates to power semiconductor devices in GaN technology. The disclosure proposes an integrated auxiliary gate terminal (15) and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device (205) and a low-voltage auxiliary GaN device (210) wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal. In other embodiments a pull-down network for the switching-off of the high threshold voltage GaN transistor is formed by a diode, a resistor, or a parallel connection of both connected in parallel with the low-voltage auxiliary GaN transistor.

First claim

1 . A III-nitride power semiconductor based heterojunction device, comprising:
an active heterojunction transistor formed on a substrate, the active heterojunction transistor comprising:
a first III-nitride semiconductor region comprising a first heterojunction comprising an active two dimensional carrier gas; a first terminal operatively connected to the III-nitride semiconductor region;
a second terminal laterally spaced from the first terminal and operatively connected to the III-nitride semiconductor region;
an active gate region formed over the III-nitride semiconductor region, the active gate region being formed between the first terminal and the second terminal;
an auxiliary heterojunction transistor formed on the said substrate or a further substrate, the auxiliary heterojunction transistor comprising:
a second III-nitride semiconductor region comprising a second heterojunction comprising an auxiliary two dimensional carrier gas;
a first additional terminal operatively connected to the second III-nitride semiconductor region;
a second additional terminal laterally spaced from the first additional terminal and operatively connected to the second III-nitride semiconductor region;
an auxiliary gate region formed over the second III-nitride semiconductor region, the auxiliary gate region being formed between the first additional terminal and the second additional terminal;
wherein the first additional terminal is operatively connected with the auxiliary gate region, and wherein the second additional terminal is operatively connected with the active gate region; and wherein the auxiliary heterojunction transistor is configured to increase a threshold voltage of said heterojunction power device and/or to increase an operation voltage range of the first additional terminal.

2 . (canceled)

3 . A heterojunction power device according to claim 1 , wherein, in use, when the first additional terminal and the auxiliary gate region are biased at a potential, the carrier density in a portion of the auxiliary two dimensional carrier gas underneath the auxiliary gate region is controlled such that an auxiliary two dimensional carrier gas connection is established between the first and second additional terminals;
optionally wherein at least one of:
(i) the active gate region is configured to be switched on through the auxiliary two dimensional carrier gas connection between the first and second additional terminals,
(ii) the first additional terminal and the auxiliary gate region are configured such that a part of the potential and hence a part of the auxiliary gate charge is used to form the auxiliary two dimensional carrier gas connection and a further part of potential is used to modulate the active gate region and the carrier density in the two dimensional carrier pas underneath the active gate region, and
(iii) the auxiliary two dimensional carrier gas connection serves as a part of the internal gate resistance to the active gate region.

4 - 6 . (canceled)

7 . A heterojunction power device according to claim 1 , wherein the first additional terminal connected with the auxiliary gate region is at a higher potential or the same potential compared to that of the second additional terminal during on-state and turn-on, and wherein the second additional terminal is at a higher potential or the same potential compared to that of the first additional terminal during off-state and turn-off.

8 . A heterojunction power device according to claim 1 , wherein at least one of (i) the first III-nitride semiconductor region comprises an active aluminium gallium nitride (AlGaN) layer directly in contact with the first terminal, the active gate region and the second terminal, and (ii) the second III-nitride semiconductor region comprises an auxiliary aluminium gallium nitride (AlGaN) layer directly in contact with the first additional terminal, the auxiliary gate region and the second additional terminal.

9 . (canceled)

10 . A heterojunction power device according to claim 8 , wherein at least one of:
(i) the thickness of the active AlGaN layer and the auxiliary AlGaN layer is the same or different, (ii) the doping concentration of the active AlGaN layer and the auxiliary AlGaN layer is the same or different, and (iii) the aluminium mole fraction of the active AlGaN layer and the auxiliary AlGaN layer may be the same or different.

11 - 12 . (canceled)

13 . A heterojunction power device according to claim 1 , wherein at least one of (i) the active gate region comprises a p-type gallium nitride (pGaN) material, and (ii) the auxiliary gate region comprises a p-type gallium nitride (pGaN) material; and
optionally wherein a metal contact on the pGaN material is a Schottky contact or an ohmic contact.

14 - 16 . (canceled)

17 . A heterojunction power device according to claim 1 , wherein at least one of (i) the auxiliary gate region comprises a recessed Schottky contact, and (ii) the active gate region comprises a recessed Schottky contact.

18 . A heterojunction power device according claim 1 , wherein either (i) the first terminal, the second terminal, the first additional terminal and the second additional terminal each comprise a surface ohmic contact or (ii) the first terminal, the second terminal, the first additional terminal and the second additional terminal each comprise a recessed ohmic contact.

19 . (canceled)

20 . A heterojunction power device according to claim 1 , wherein the auxiliary gate region comprises a field plate extending towards the first additional terminal and wherein the field plate extends over a dielectric region.

21 . A heterojunction power device according to claim 1 , wherein the device has an interdigitated layout in which at least one of (i) a gate metal pad is directly connected with the auxiliary gate region and the first additional terminal, and wherein the active gate region comprises gate fingers connected with the second additional terminal and (ii) the device has an interdigitated layout in which the auxiliary gate region, the first additional terminal and the second additional terminal are placed below a source metal pad; and
optionally wherein the distance between the auxiliary gate region and first or second additional terminal is adjustable to control a gate resistance in the auxiliary heterojunction transistor and the active heterojunction transistor.

22 - 23 . (canceled)

24 . A heterojunction power device according to claim 1 , wherein the second additional terminal and the active gate region are connected in a third dimension of the device.

25 . A heterojunction power device according to claim 1 , further comprising an additional auxiliary heterojunction transistor or several such additional auxiliary heterojunction transistors in series, optionally further comprising a further isolator region between the auxiliary heterojunction transistor and the additional auxiliary heterojunction transistor.

26 . (canceled)

27 . A heterojunction power device according to claim 1 , wherein the active heterojunction transistor is a high voltage transistor and the auxiliary heterojunction transistor is a low voltage transistor compared to the active heterojunction transistor.

28 . A heterojunction power device according to claim 1 , further comprising a diode connected in parallel between the first and second additional terminals of the auxiliary heterojunction transistor, optionally wherein at least one of:
(i) wherein the diode is

Assignees

• Cambridge Entpr Ltd

Inventors

• Udrea Florin
• Efthymiou Loizos
• Longobardi Giorgia

Classifications

• H01L29/872

  Electricity · mapped topic

• H01L27/0629

  Electricity · mapped topic

• H01L29/41758

  Electricity · mapped topic

• H01L29/7786

  Electricity · mapped topic

• H01L29/205

  Electricity · mapped topic