Display apparatus and method of controlling display apparatus

Patent metadata

Field	Value
Publication number	US-2020168172-A1
Application number	US-201916689903-A
Country	US
Kind code	A1
Filing date	Nov 20, 2019
Priority date	Nov 28, 2018
Publication date	May 28, 2020
Grant date	—

Abstract

A display apparatus is disclosed. The display apparatus according to one Embodiment comprises: a plurality of pixels arranged in a matrix; a plurality of scanning lines; a plurality of data lines; a scanning line drive unit to generate a scanning signal for selecting a group of pixels arranged in the row direction based on a scanning clock signal and successively output the generated scanning signal to the plurality of scanning lines; a data line drive unit to output, to a plurality of data lines, data signals for supplying voltages to the group of pixels arranged in the row direction; and a timing control unit to control the drive timing of the scanning line drive unit and the data line drive unit based on a first clock signal, and to generate the scanning clock signal based on the first clock signal.

First claim

What is claimed is:

1 . A display apparatus, comprising:
a plurality of pixels arranged in a matrix; a plurality of scanning lines each connected to a group of pixels arranged in a row direction of the plurality of pixels; a plurality of data lines each connected to a group of pixels arranged in a column direction of the plurality of pixels; a scanning line drive unit to generate a scanning signal for selecting the group of pixels arranged in the row direction based on a scanning clock signal and successively output the generated scanning signal to the plurality of scanning lines, wherein the scanning clock signal indicates the drive timing of the plurality of scanning lines; a data line drive unit to output, to the plurality of data lines, data signals for supplying voltages to the group of pixels arranged in the row direction, wherein the group of pixels is selected by the scanning signal, and the voltages are based on video data; and a timing control unit to control the drive timing of the scanning line drive unit and the data line drive unit based on a first clock signal, and to generate the scanning clock signal based on the first clock signal; wherein the timing control unit comprises: a delay amount acquisition unit to acquire a delay amount at the time of level transition of the scanning clock signal relative to the time of level transition of a base timing signal, level transition from a first signal level to a second signal level of which is repeated in synchronization with the first clock signal at a period corresponding to one horizontal scanning period; a first timing generation unit to generate a first timing signal which delays the time of level transition of the base timing signal by a delay corresponding to a period unit of the first clock signal of the delay amount based on the first clock signal; a second timing generation unit to generate at least one second timing signal which delays the time of level transition of the first timing signal by a duration of a period unit of a second clock signal having frequency higher than frequency of the first clock signal; and a selection unit to output one timing signal as the scanning clock signal, wherein the one timing signal is selected from the first timing signal and the at least one second timing signal based on the delay amount.

2 . The display apparatus according to claim 1 , wherein
the delay amount acquisition unit acquires the delay amount for each of the plurality of scanning lines, the first timing signal generation unit delays the time of level transition indicating the drive timing of one scanning line in the base timing signal by a delay corresponding to the period unit of the first clock signal of the delay amount for the one scanning line to generate the first timing signal, and the selection unit outputs the one timing signal selected based on the delay amount for the one scanning line as a signal indicating the drive timing of the one scanning line in the scanning clock signal.

3 . The display apparatus according to claim 1 , further comprising a multiplication unit to multiply the first clock signal to generate the second clock signal.

4 . The display apparatus according to claim 1 , wherein
the second timing signal generation unit comprises a serially-connected plurality of delay elements, and the at least one second timing signal comprises a plurality of second timing signals and the plurality of second timing signals respectively generated by the plurality of delay elements are input into the selection unit.

5 . The display apparatus according to claim 4 , wherein the plurality of delay elements respectively delay signals input into the plurality of delay elements by one period of the second clock signal.

6 . The display apparatus according to claim 1 , wherein the first timing signal generation unit delays the base timing signal based on information obtained by rounding at least one less significant bit of information on the delay amount to generate the first timing signal.

7 . The display apparatus according to claim 6 , wherein the selection unit selects the one timing signal based on information on the at least one less significant bit.

8 . The display apparatus according to claim 1 , further comprising a horizontal counter unit and a vertical counter unit to respectively count the number of pulses of a horizontal synchronization signal and a vertical synchronization signal being in synchronization with video data corresponding to video to be displayed on a display panel comprising the plurality of pixels,
wherein the delay amount acquisition unit acquires the delay amount based on the number of pulses of the horizontal synchronization signal and the vertical synchronization signal.

9 . A method of controlling a display apparatus, the display apparatus comprising: a plurality of pixels arranged in a matrix; a plurality of scanning lines each connected to a group of pixels arranged in a row direction of the plurality of pixels; a plurality of data lines each connected to a group of pixels arranged in a column direction of the plurality of pixels; a scanning line drive unit to generate a scanning signal for selecting the group of pixels arranged in the row direction based on a scanning clock signal and successively output the generated scanning signal to the plurality of scanning lines, wherein the scanning clock signal indicates the drive timing of the plurality of scanning lines; a data line drive unit to output, to the plurality of data lines, data signals for supplying voltages to the group of pixels arranged in the row direction, wherein the group of pixels is selected by the scanning signal, and the voltages are based on video data; and a timing control unit to control the drive timing of the scanning line drive unit and the data line drive unit based on a first clock signal, and to generate the scanning clock signal based on the first clock signal, the method of controlling a display apparatus comprising:
acquiring a delay amount at the time of level transition of the scanning clock signal relative to the time of level transition of a base timing signal, level transition from a first signal level to a second signal level of which is repeated in synchronization with the first clock signal at a period corresponding to one horizontal scanning period; generating a first timing signal which delays the time of level transition of the base timing signal by a delay corresponding to a period unit of the first clock signal of the delay amount based on the first clock signal; generating at least one second timing signal which delays the time of level transition of the first timing signal by a duration of a period unit of a second clock signal having frequency higher than frequency of the first clock signal; and outputting one timing signal as the scanning clock signal, wherein the one timing signal is selected from the first timing signal and the at least one second timing signal based on the delay amount.

Assignees

• Sakai Display Products Corp

Inventors

• Sawahata Junichi

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G3/3696

  Generation of voltages supplied to electrode drivers · CPC title

• G09G3/3688

  suitable for active matrices only · CPC title

• G09G3/3648 Primary

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title