Component Carrier Comprising a Photo-Imageable Dielectric and Method of Manufacturing the Same

Patent metadata

Field	Value
Publication number	US-2020163218-A1
Application number	US-201916689511-A
Country	US
Kind code	A1
Filing date	Nov 20, 2019
Priority date	Nov 20, 2018
Publication date	May 21, 2020
Grant date	—

Abstract

A method of manufacturing a component carrier is disclosed. The method includes forming a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; patterning a front side of the stack using a first photo-imageable dielectric; and patterning a back side of the stack. A component carrier is also disclosed.

First claim

1 . A method of manufacturing a component carrier, comprising:
forming a stack comprising at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; patterning a front side of the stack using a first photo-imageable dielectric; and patterning a back side of the stack.

2 . The method according to claim 1 , wherein patterning the front side of the stack using a first photo-imageable dielectric comprises illumination with electromagnetic radiation through a mask, followed by developing of the illuminated first photo-imageable dielectric, followed in turn by a selective removal of either the illuminated portion or the non-illuminated portion of the developed first photo-imageable dielectric.

3 . The method according to claim 1 , wherein the first photo-imageable dielectric is patterned for contacting embedded components having different distances between the front side and an upper main surface of the respective component.

4 . The method according to claim 1 , further comprising:
patterning the back side of the stack by laser drilling.

5 . The method according to claim 1 , wherein a through-hole composed of a first hole portion with straight sidewalls on the front side connected to a second hole portion with tapering sidewalls on the backside is formed.

6 . The method according to claim 1 , wherein patterning the front side of the stack using the first photo-imageable dielectric comprises forming multiple holes on the front side with different vertical depths.

7 . The method according to claim 1 , wherein patterning the back side of the stack comprises forming multiple holes on the back side with substantially the same vertical depth.

8 . The method according to claim 1 , wherein patterning the front side of the stack using the first photo-imageable dielectric comprises forming multiple holes on the front side with different horizontal widths.

9 . The method according to claim 1 , further comprising:
forming a wire and/or a coax cable in a hole or a via or of the component carrier.

10 . The method according to claim 1 , wherein a metal core is provided, to which the first photo-imageable dielectric is applied.

11 . The method according to claim 1 , wherein forming the stack comprises forming a dielectric core with metallized sidewalls.

12 . The method according to claim 1 , wherein forming the stack comprises forming a through-hole formed by the first photo-imageable dielectric on the front side, by a dielectric on the backside, and by laser processing from the backside.

13 . The method according to claim 12 , wherein the dielectric on the backside is a thermal curing material or a second photo-imageable dielectric.

14 . The method according to claim 1 , wherein forming the stack comprises the steps of:
providing a metal core; attaching a temporary carrier on a backside of the metal core; forming a first cavity into the metal core; embedding a semiconductor chip and/or a passive component into the first cavity; applying the first photo-imageable dielectric on a front side of the metal core; patterning the first photo-imageable dielectric at the first cavity for contacting the embedded semiconductor chip and/or the passive component, thereby forming holes on the front side; removing the temporary carrier from the backside of the metal core; applying a dielectric on a backside of the metal core; patterning the dielectric on the backside at the first cavity, thereby forming holes on the back side; and plating or filling the holes by a metal.

15 . The method according to claim 14 , wherein before patterning the dielectric on the backside at the first cavity, at least one metal layer is applied onto the backside of the metal core, the metal layer is patterned, and the dielectric is applied on the at least one patterned metal layer.

16 . The method according to claim 14 , further comprising:
forming a second cavity into the metal core; patterning the first photo-imageable dielectric at the second cavity, thereby forming holes on the front side; patterning the dielectric on the backside at the second cavity, thereby forming holes on the back side; and plating or filling the holes by a metal.

17 . A component carrier, comprising:
a stack comprising at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; at least one hole with straight sidewalls on a front side of the stack; and at least one hole with tapering sidewalls on a back side of the stack.

18 . The component carrier according to claim 17 , further comprising:
a cured patterned first photo-imageable dielectric on the front side of the stack; and at least one cone-shaped hole on the back side of the stack.

19 . A component carrier, comprising:
a stack comprising at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; a cured patterned first photo-imageable dielectric on a front side of the stack; and at least one cone-shaped hole on a back side of the stack.

20 . The component carrier according to claim 19 , further comprising:
a cured patterned dielectric on the back side of the stack.

21 . The component carrier according to claim 20 , wherein the dielectric on the backside is a thermal curing material or a second photo-imageable dielectric.

22 . The component carrier according to claim 17 , further comprising at least one of the following features:
the component carrier comprises a metal core having a first cavity, in which a semiconductor chip and/or a passive component is accommodated; the component carrier further comprises a through-hole passing the component carrier; a hole extending from the front side has sidewalls being at least partially covered with the cured first photo-imageable dielectric; an inner surface of the hole and/or the through-hole is plated or filled by a metal; the component carrier further comprises a component, in particular an electronic component, mounted on and/or embedded in the at least one electrically insulating layer structure and/or the at least one electrically conductive layer structure.

23 . The component carrier according to claim 22 , wherein the component is selected from a group consisting of an electronic component, an electrically non-conductive and/or electrically conductive inlay, a heat transfer unit, a light guiding element, an energy harvesting unit, an active electronic component, a passive electronic component, an electronic chip, a storage device, a filter, an integrated circuit, a signal processing component, a power management component, an optoelectronic interface element, a voltage converter, a cryptographic component, a transmitter and/or receiver, an electromechanical transducer, an actuator, a microelectromechanical system, a microprocessor, a capacitor, a resistor, an inductance, an accumulator, a switch, a camera, an antenna, a magnetic element, a further component carrier and a logic chip.

24 . The component carrier according to claim 17 , further comprising at least one of the following features:
the at least one electrically conductive layer structure comprises at least one of the group consisting of copper, aluminum, nickel, silver, gold, palladium, and tungsten, any of the mentioned materials being optionally coated with supra-conductive material such as graphene; the at lea

Assignees

• At & S Austria Tech & Systemtechnik Ag

Inventors

• Mok Jeesoo

Classifications

• H05K1/0204

  using means for thermal conduction connection in the thickness direction of the substrate (H05K1/0207 takes precedence) · CPC title

• G03F7/20

  Exposure; Apparatus therefor (photographic printing apparatus for making copies G03B27/00) · CPC title

• H05K1/05

  Insulated {conductive substrates, e.g. insulated} metal substrate · CPC title

• H05K1/186

  manufactured by mounting on or connecting to patterned circuits before or during embedding · CPC title

• H05K3/4038

  Through-connections; Vertical interconnect access [VIA] connections (H05K3/403, H05K3/42 take precedence) · CPC title