Three-dimensional semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2020161330-A1
Application number	US-202016750176-A
Country	US
Kind code	A1
Filing date	Jan 23, 2020
Priority date	Nov 7, 2017
Publication date	May 21, 2020
Grant date	—

Abstract

A three-dimensional semiconductor memory device includes a peripheral logic structure on a semiconductor substrate. A horizontal semiconductor layer is on the peripheral logic structure and includes a cell array region and a connection region. Electrode structures extend in a first direction on the horizontal semiconductor layer and are spaced apart in a second direction intersecting the first direction. A pair of the electrode structures adjacent to each other are symmetrically disposed to define a contact region partially exposing the horizontal semiconductor layer. A through via structure is on the contact region and connects the electrode structures to the peripheral logic structure. Each of the electrode structures includes a plurality of gate insulation regions extending along the first direction on the connection region. The gate insulation regions have different lengths from each other in the first direction.

First claim

What is claimed is:

1 . A three-dimensional semiconductor memory device, comprising:
a peripheral logic structure on a semiconductor substrate; a horizontal semiconductor layer on the peripheral logic structure and including a cell array region and a connection region; electrode structures extending in a first direction on the horizontal semiconductor layer and spaced apart in a second direction crossing the first direction, the electrode structures including electrodes vertically stacked on the horizontal semiconductor layer; electrode isolation regions disposed between the electrode structures and extending from the cell array region to the connection region; gate insulating regions crossing the electrodes of the electrode structures in the first direction; an opening crossing at least one of the electrodes in a second direction and connecting the gate insulation regions; an insulating layer filling the opening; a through insulation pattern penetrating the horizontal semiconductor layer between two electrode isolation regions adjacent to each other among the electrode isolation regions; and and through plugs penetrating the through insulation pattern and connected to the peripheral logic structure.

2 . The device of claim 1 , wherein the electrode isolation regions has a length in the first direction longer than the gate insulation regions.

3 . The device of claim 1 , wherein the opening penetrates a lowermost electrode of the electrodes.

4 . The device of claim 1 , wherein the insulating layer covers a top surface of a lowermost electrode of the electrodes.

5 . The device of claim 1 , wherein the insulating layer includes silicon oxide.

6 . The device of claim 1 , wherein the through plugs are disposed between the gate insulation region and the electrode isolation region.

7 . The device of claim 1 , wherein the electrode isolation regions extend along paths that are parallel to each other.

8 . The device of claim 1 , wherein the through plugs electrically connect the electrode structure and the peripheral logic structure.

9 . The device of claim 1 , further comprising vertical semiconductor patterns vertically penetrating the electrode structure on the substrate of the cell array region.

10 . The device of claim 1 , further comprising contact plugs respectively connected to the electrodes on the connection area of the substrate.

11 . A three-dimensional semiconductor memory device, comprising:
a peripheral logic structure on a semiconductor substrate; a horizontal semiconductor layer on the peripheral logic structure and including a cell array region and a connection region; a first electrode structure and a second electrode structure extending in a first direction on the horizontal semiconductor layer, each of the first and second electrode structures comprising electrodes vertically stacked on the horizontal semiconductor layer; electrode isolation regions disposed between the first and second electrode structures and extending from the cell array region to the connection region; a gate insulating regions crossing the electrodes of the first electrode structure in the first direction; an opening crossing at least one of the electrodes of the first electrode structure in a second direction crossing the first direction, the opening connected to the gate insulating region; an insulating layer filling the opening; a first through via structure penetrating the first electrode structure and connected to the peripheral logic structure; and a second through via structure penetrating the second electrode structure and connected to the peripheral logic structure, the second through via structure spaced apart from the first through via structure with the electrode isolation region therebetween.

12 . The device of claim 11 , wherein the first through via structure disposed between the gate insulating regions and the electrode isolation region.

13 . The device of claim 11 , wherein the electrode isolation regions has a length in the first direction longer than the gate insulation region.

14 . The device of claim 11 , wherein the insulating layer covers a top surface of a lowermost electrode of the electrodes.

15 . The device of claim 11 , wherein each of the first and second through via structures comprises:
a through insulation pattern extending in a third direction perpendicular to a top surface of the horizontal semiconductor layer and penetrating the horizontal semiconductor layer; through plugs penetrating the through insulation pattern and connected to the peripheral logic structure.

16 . The device of claim 11 , wherein the first and second through via structures are located on the connection region.

17 . The device of claim 11 , wherein the gate insulating regions are located on the connection region.

18 . The device of claim 11 , wherein the opening is located between the first through via structure and the cell array region.

19 . The device of claim 1 , further comprising vertical semiconductor patterns vertically penetrating the electrode structure on the substrate of the cell array region.

20 . The device of claim 1 , further comprising contact plugs respectively connected to the electrodes on the connection area of the substrate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kanamori Kohji
• Kang Seo-Goo
• Son Younghwan
• Jo Kwonsoon

Classifications

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• H01L27/11573

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic