Memory device

Patent metadata

Field	Value
Publication number	US-2020161329-A1
Application number	US-202016747866-A
Country	US
Kind code	A1
Filing date	Jan 21, 2020
Priority date	Jul 20, 2016
Publication date	May 21, 2020
Grant date	—

Abstract

A memory device includes gate electrode layers stacked on an upper surface of a substrate and each including a plurality of unit electrodes extending in a first direction, and a plurality of connecting electrodes connecting the unit electrodes to each other. The memory device also includes channel structures extending through the gate electrode layers in a direction perpendicular to the upper surface of the substrate, first common source lines extending in the first direction and interposed between the unit electrodes, and second common source lines extending in the first direction between the first common source lines and each having a first line and a second line separated from each other in the first direction by the connecting electrodes.

First claim

What is claimed is:

1 . A memory device, comprising:
a plurality of gate electrode layers stacked on a substrate; a plurality of channel structures penetrating the plurality of gate electrode layers; a plurality of first wordline cuts extending in a first direction parallel to an upper surface of the substrate to divide the plurality of gate electrode layers, and separated from each other in a second direction intersecting the first direction; a plurality of second wordline cuts disposed between a pair of the first wordline cuts, among the plurality of the first wordline cuts, being adjacent to each other in the second direction; and a plurality of isolation insulating layers disposed between the pair of the first wordline cuts and dividing each of the plurality of second wordline cuts into a first line and a second line, in the first direction, wherein a pair of the isolation insulating layers, among the plurality of isolation insulating layers, being closest to each other in the second direction, are not overlapped to each other in the second direction.

2 . The memory device of claim 1 , wherein the pair of the isolation insulating layers have substantially the same length in the first direction.

3 . The memory device of claim 1 , wherein the plurality of isolation insulating layers comprises a first isolation insulating layer, a second isolation insulating layer and a third isolation insulating layer sequentially disposed along the second direction, and
the first isolation insulating layer and the third isolation insulating layer are overlapped each other in the second direction.

4 . The memory device of claim 3 , wherein the first isolation insulating layer, the second isolation insulating layer and the third isolation insulating layer are disposed in a zigzag form.

5 . The memory device of claim 3 , wherein a first cell contact is disposed between the first isolation insulating layer and the second isolation insulating layer, and a second cell contact is disposed between the second isolation insulating layer and the third isolation insulating layer, and
a length of the first cell contact is substantially equal to a length of the second cell contact, in a third direction perpendicular to the upper surface of the substrate.

6 . The memory device of claim 3 , further comprising:
a plurality of dummy channel structures penetrating at least a portion of the plurality of gate electrode layers, wherein at least one of the plurality of dummy channel structures are disposed between the first isolation insulating layer and the second line, in the second direction.

7 . The memory device of claim 6 , wherein two or more of the plurality of dummy channel structures are disposed between the first isolation insulating layer and the second line, in the second direction.

8 . The memory device of claim 6 , wherein at least a portion of the plurality of dummy channel structures are disposed at both sides of one end of the first isolation insulating layer, in the second direction.

9 . A memory device, comprising:
a plurality of gate electrode layers stacked on a substrate; a plurality of channel structures penetrating the plurality of gate electrode layers; a plurality of first wordline cuts extending in a first direction parallel to an upper surface of the substrate to divide the plurality of gate electrode layers, and separated from each other in a second direction intersecting the first direction; a plurality of second wordline cuts disposed between a pair of the first wordline cuts, among the plurality of the first wordline cuts, being adjacent to each other in the second direction; and a plurality of isolation insulating layers disposed between the pair of the first wordline cuts and dividing each of the plurality of second wordline cuts into a plurality of lines, in the first direction, wherein the plurality of isolation insulating layers comprises a first isolation insulating layer, a second isolation insulating layer and a third isolation insulating layer sequentially disposed along the second direction, the first isolation insulating layer and the third isolation insulating layer are overlapped in the second direction, and the first isolation insulating layer and the second isolation insulating layer are not overlapped in the second direction, and the first isolation insulating layer and the second isolation insulating layer are isolation insulating layers closest in the second direction, and the second isolation insulating layer and the third isolation insulating layer are isolation insulating layers closest in the second direction.

10 . The memory device of claim 9 , wherein a second line among a first line and the second line separated from each other by the first isolation insulating layer has the same length with a fourth line, in the first direction, among a third line and the fourth line separated from each other by the third isolation insulating layer, and
a sixth line among a fifth line and the sixth line separated from each other by the second isolation insulating layer has a different length from the second line, in the first direction.

11 . The memory device of claim 9 , further comprising:
a plurality of dummy channel structures penetrating at least a portion of the plurality of gate electrode layers, wherein each of the plurality of isolation insulating layers has a first end and a second end opposite to each other in the first direction, and the first end is adjacent to at least one of the plurality of dummy channel structures in the second direction.

12 . The memory device of claim 11 , further comprising:
a plurality of cell contacts connected the plurality of gate electrode layers, wherein the second end of each of the plurality of isolation insulating layers is adjacent to at least one of the plurality of cell contacts in the second direction.

13 . The memory device of claim 11 , wherein the second end of the first isolation insulating layer and the second end of the second isolation insulating layer are disposed at substantially same position, in the first direction.

14 . The memory device of claim 11 , wherein the first end of the first isolation insulating layer and the first end of the third isolation insulating layer are disposed at substantially same position, in the first direction.

15 . The memory device of claim 9 , further comprising:
a plurality of common source lines extending in the first direction, in the plurality of first wordline cuts and the plurality of second wordline cuts.

16 . A memory device, comprising:
a substrate having a cell region and a peripheral region; a plurality of gate electrode layers stacked on the substrate; a plurality of channel structures penetrating the plurality of gate electrode layers, in the cell region; a plurality of first wordline cuts extending in a first direction parallel to an upper surface of the substrate to divide the plurality of gate electrode layers, and separated from each other in a second direction intersecting the first direction; a plurality of second wordline cuts disposed between a pair of the first wordline cuts, among the plurality of the first wordline cuts, being adjacent to each other in the second direction; and a plurality of isolation insulating layers disposed between the pair of the first wordline cuts and dividing each of the plurality of second wordline cuts into a first line and a second line, in the first direction, wherein the plurality of isolation insulating layers comprises a first isolation insulating layer, a second isolation insu

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Su Jin
• Kim Sun Young
• Yun Jang Gn

Classifications

• H01L23/528

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic