Integrated circuit including standard cells overlapping each other and method of generating layout of the integrated circuit

Patent metadata

Field	Value
Publication number	US-2020159984-A1
Application number	US-202016750501-A
Country	US
Kind code	A1
Filing date	Jan 23, 2020
Priority date	Jun 14, 2017
Publication date	May 21, 2020
Grant date	—

Abstract

Provided is an integrated circuit including a plurality of standard cells each including a front-end-of-line (FEOL) region and a back-end-of-line (BEOL) region on the FEOL region, the FEOL region including at least one gate line extending in a first horizontal direction. A BEOL region of a first standard cell among the plurality of standard cells includes an eaves section not overlapping an FEOL region of the first standard cell in a vertical direction, the eaves section protruding in a second horizontal direction perpendicular to the first horizontal direction.

First claim

What is claimed is:

1 . An integrated circuit comprising:
a first standard cell including a first front-end-of-line (FEOL) region and a first back-end-of-line (BEOL) region, wherein the first FEOL region includes at least one gate line extending in a first horizontal direction and at least one fin extending in a second horizontal direction crossing the first horizontal direction, and
the first BEOL region includes a first pattern extending in the first horizontal direction and overlapping a boundary of the first FEOL region in a vertical direction.

2 . The integrated circuit of claim 1 , wherein the first pattern is an input pin or an output pin of the first standard cell.

3 . The integrated circuit of claim 1 , wherein the first BEOL region includes an eaves section protruding in the second horizontal direction and not overlapping the first FEOL region in the vertical direction, and
the eaves section includes at least part of the first pattern.

4 . The integrated circuit of claim 3 , further comprising:
a second standard cell adjacent to the first standard cell in the second horizontal direction, wherein the second standard cell includes a second FEOL region and a second BEOL region, and
the second FEOL region includes a first step section overlapping the eaves section of the first standard cell in the vertical direction and protruding in direction antiparallel to the second horizontal direction.

5 . The integrated circuit of claim 4 , further comprising:
a single diffusion break extending in the first horizontal direction between the first FEOL region and the second FEOL region.

6 . The integrated circuit of claim 4 , wherein the second BEOL region includes an eaves section protruding in the second horizontal direction and not overlapping the second FEOL region of the second standard cell in the vertical direction, and
a length of the eaves section of the second standard cell in the second horizontal direction is the same as a length of the first step section in the second horizontal direction.

7 . The integrated circuit of claim 4 , wherein the second FEOL region further includes a second step section protruding in the second horizontal direction and not overlapping the second BEOL region in the vertical direction, and
a length of the second step section in the second horizontal direction is the same as a length of the first step section in the second horizontal direction.

8 . The integrated circuit of claim 7 , further comprising:
a third standard cell adjacent to the second standard cell in the second horizontal direction, wherein the third standard cell includes a third FEOL region and a third BEOL region, and
the third BEOL region includes an eaves section protruding in a direction antiparallel to the second horizontal direction and overlapping the second step section in the vertical direction.

9 . The integrated circuit of claim 3 , further comprising:
a second standard cell adjacent to the first standard cell in the second horizontal direction, wherein the second standard cell includes a second FEOL region and a second BEOL region, and
the second BEOL region includes an eaves section protruding in a direction antiparallel to the second horizontal direction and not overlapping the second FEOL region in the vertical direction.

10 . The integrated circuit of claim 9 , further comprising:
a double diffusion break extending in the first horizontal direction between the first FEOL region and the second FEOL region, wherein the double diffusion break overlaps the eaves sections of the first and second standard cells in the vertical direction.

11 . The integrated circuit of claim 3 , wherein the first FEOL region includes a step section protruding in a direction antiparallel to the second horizontal direction and not overlapping the first BEOL region in the vertical direction, and
a length of the step section of the first standard cell in the second horizontal direction is the same as a length of the eaves section of the first standard cell in the second horizontal direction.

12 . The integrated circuit of claim 11 , further comprising:
a second standard cell adjacent to the first standard cell in direction antiparallel to the second horizontal direction, and wherein the second standard cell includes a second FEOL region and a second BEOL region, and
the second FEOL region includes a step section protruding in the second horizontal direction and not overlapping the second BEOL region in the vertical direction.

13 . The integrated circuit of claim 12 , further comprising:
a single diffusion break extending in the first horizontal direction between the first FEOL region and the second FEOL region.

14 . The integrated circuit of claim 12 , further comprising:
at least one pattern extending in the second horizontal direction between the BEOL region of the first standard cell and the BEOL region of the second standard cell and connecting power lines of the first and second standard cells.

15 . The integrated circuit of claim 11 , further comprising:
a second standard cell adjacent to the first standard cell in direction antiparallel to the second horizontal direction, wherein the second standard cell includes a second FEOL region and a second BEOL region,
the second BEOL region comprises a first eaves section and a second eaves section which do not overlap the second FEOL region in the vertical direction,
the first and second eaves sections respectively protrude in the second horizontal direction and the direction antiparallel to the second horizontal direction and have the same length in the second horizontal direction, and
the first eaves section overlaps the step section of the first standard cell in the vertical direction.

16 . The integrated circuit of claim 15 , further comprising:
a third standard cell adjacent to the second standard cell in direction antiparallel to the second horizontal direction, wherein the third standard cell includes a third FEOL region and a third BEOL region, the third FEOL region includes a step section protruding in the second horizontal direction and overlapping the second eaves section in the vertical direction.

17 . The integrated circuit of claim 11 , wherein the first FEOL region further comprises at least one transistor and at least one contact structure configured to transmit a power supply voltage to the at least one transistor, and
the at least one contact structure is adjacent to the step section of the first standard cell.

18 . The integrated circuit of claim 3 , further comprising:
a second standard cell symmetrical with the first standard cell with respect to an axis parallel with the first horizontal direction, the second standard cell providing the same function as the first standard cell, and wherein a BEOL region of the second standard cell comprises an eaves section protruding in a direction antiparallel to the second horizontal direction.

19 . The integrated circuit of claim 3 , further comprising:
a second standard cell including a second FEOL region and a second BEOL region which are stacked in the same size and manner as the first FEOL and the second BEOL region, wherein the second standard cell having a pin placement that is different from a pin placement of the first standard cell.

20 . The integrated circuit of claim 19 , wherein the second FEOL region is symmetrical with the first FEOL region with respect to an axis parallel with the first horizontal di

Assignees

• Samsung Electronics Co Ltd

Inventors

• Do Jung-Ho
• Jung Jong-Hoon
• Yu Ji-Su
• Lee Seung-Young
• Song Tae-Joong
• Lee Jae-Boong

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H01L27/0207

  Electricity · mapped topic

• H01L27/11807

  Electricity · mapped topic

• H10D89/10 Primary

  Integrated device layouts · CPC title