Semiconductor memory device and memory system having the same

Patent metadata

Field	Value
Publication number	US-2020159617-A1
Application number	US-201916377183-A
Country	US
Kind code	A1
Filing date	Apr 6, 2019
Priority date	Nov 19, 2018
Publication date	May 21, 2020
Grant date	—

Abstract

Disclosed are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes a memory cell array having a plurality of memory cells and includes an error correcting code (ECC) decoder configured to receive first data and a first parity for the first data from selected memory cells of the memory cell array, generate a second parity for the first data using an H-matrix and the first data, compare the first parity to the second parity to generate a first syndrome, and generate a decoding status flag (DSF) with different states on the basis of a number of “0” or “1” bits included in the first syndrome.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a row decoder configured to decode a row address to generate a plurality of word line selection signals; a column decoder configured to decode a column address to generate a plurality of column selection signals; a memory cell array comprising a plurality of memory cells, one or more of the plurality memory cells being selected in response to the a plurality of word line selection signals and the a plurality of column selection signals; and an error correcting code (ECC) decoder configured to: receive first data and a first parity for the first data from the selected memory cells of the memory cell array, generate a second parity for the first data using an H-matrix and the first data, compare the first parity to the second parity to generate a first syndrome, and generate a decoding status flag (DSF) with different states on the basis of the number of “0” or “1” included in the first syndrome.

2 . The semiconductor memory device of claim 1 , wherein codes of column vectors of the H-matrix are different codes from each other, and
wherein each of the codes includes bits of “0” and “1” except for a code of including all “0” bits.

3 . The semiconductor memory device of claim 2 , wherein a minimum hamming distance between the codes of the H-matrix is greater than or equal to three.

4 . The semiconductor memory device of claim 2 , wherein the ECC decoder is configured to:
activate a non-error signal in response to the first syndrome having all bits of “0,” activate a correctable error signal in response to the first syndrome having a number of “1” bits less than or equal to a predetermined number, and activate an uncorrectable error signal in response to the first syndrome having a number of “1” bits greater than the predetermined number.

5 . The semiconductor memory device of claim 4 , wherein the ECC decoder comprises a parity generator configured to perform an exclusive OR (XOR) operation on each of codes of row vectors of the H-matrix and the first data and a modulo 2 operation thereon to generate the second parity.

6 . The semiconductor memory device of claim 5 , wherein the ECC decoder further comprises:
a syndrome generator configured to perform an XOR operation on the first parity and the second parity to generate the first syndrome; and an error detector configured to activate the non-error signal, the correctable error signal, or the uncorrectable error signal in response to the first syndrome.

7 . The semiconductor memory device of claim 6 , wherein the ECC decoder further comprises:
an error position detector configured to detect which of the codes of the column vectors of the H-matrix match the first syndrome to generate error position information in response to the activating of the correctable error signal; an error corrector configured to correct an error of a corresponding position of the first data on the basis of the error position information in response to the activating of the correctable error signal; and a DSF generator configured to generate the DSF with different states in response to either the activating of the non-error signal or the correctable error signal or the activating of the uncorrectable error signal.

8 . A semiconductor memory device comprising:
a row decoder configured to decode a row address to generate a plurality of word line selection signals; a column decoder configured to decode a column address to generate a plurality of column selection signals; a memory cell array including a plurality of memory cells, one or more of the plurality of memory cells being selected in response to the plurality of word line selection signals and the plurality of column selection signals; and an error correcting code (ECC) decoder configured to: receive first data and a first parity for the first data output from the selected memory cells of the memory cell array, generate a second parity for the first data using a first H-matrix and the first data, compare the first parity to the second parity to generate a first syndrome, compare two adjacent bits of the first syndrome to generate a second syndrome, and generate a decoding status flag (DSF) with different states using the second syndrome and a second H-matrix, wherein first codes of column vectors of the first H-matrix are included in second codes of column vectors of the second H-matrix, which is generated by performing an exclusive OR (XOR) operation on the two adjacent bits of each of the first codes.

9 . The semiconductor memory device of claim 8 , wherein the first codes are different codes from each other, and each of the first codes includes bits of “0” and “1” except for a code including all “0” bits.

10 . The semiconductor memory device of claim 9 , wherein a minimum hamming distance between the first codes is greater than or equal to three.

11 . The semiconductor memory device of claim 9 , wherein the ECC decoder is configured to:
activate a non-error signal in response to the second syndrome having all bits of “0,” activate a correctable error signal in response to the second syndrome being present in the second codes, and activate an uncorrectable error signal in response to the second syndrome not being present in the second codes.

12 . The semiconductor memory device of claim 11 , wherein the ECC decoder comprises a first parity generator configured to perform an XOR operation on each of codes of row vectors of the first H-matrix and the first data and a modulo 2 operation thereon to generate the second parity.

13 . The semiconductor memory device of claim 12 , wherein the ECC decoder further comprises:
a syndrome generator configured to perform an XOR operation on the first parity and the second parity to generate the first syndrome; a comparator configured to perform an XOR operation on two adjacent bits of the first syndrome to generate the second syndrome; and an error detector configured to activate the non-error signal, the correctable error signal, and the uncorrectable error signal in response to the second syndrome.

14 . The semiconductor memory device of claim 13 , wherein the ECC decoder further comprises:
an error position detector configured to detect which of the first codes match the first syndrome to generate error position information in response to the activating of the correctable error signal; an error corrector configured to correct an error of a corresponding position of the first data on the basis of the error position information in response to the activating of the correctable error signal; and a DSF generator configured to generate the DSF with different states in response to either the activating of the non-error signal or the correctable error signal or the activating of the uncorrectable error signal.

15 . A memory system comprising:
a semiconductor memory device comprising:
a row decoder configured to decode a row address to generate a plurality of word line selection signals;
a column decoder configured to decode a column address to generate a plurality of column selection signals;
a memory cell array including a plurality of memory cells, one or more of the plurality of memory cells being selected in response to the plurality of word line selection signals and the plurality of column selection signals; and
a first error correcting code (ECC) decoder configured to:
receive first data and a first parity for the first data from the selected memory cells of the memory cell array,
generate a second parity for the first data using a first H-matrix and t

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cha Sang Uhn
• Kim Hyun Gi

Classifications

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G06F11/1012 Primary

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title