Array substrate, manufacturing method thereof and display panel

Patent metadata

Field	Value
Publication number	US-2020144296-A1
Application number	US-201916504780-A
Country	US
Kind code	A1
Filing date	Jul 8, 2019
Priority date	Nov 1, 2018
Publication date	May 7, 2020
Grant date	—

Abstract

An array substrate is provided that includes a plurality of sub-pixels arranged in a matrix. Each of the sub-pixels includes a substrate, a gate, a source and a drain, and a common electrode on the substrate, a passivation layer on a side of the common electrode facing away from the substrate, and a pixel electrode on a side of the passivation layer facing away from the substrate. The array substrate further includes a common electrode line, the common electrode line being formed of a same material in a same layer as the source and the drain. The common electrode is in direct electrical contact with the common electrode line. The pixel electrode and the drain are electrically connected through a via hole in the passivation layer. A display panel and a method for manufacturing an array substrate are further provided.

First claim

1 . An array substrate comprising a plurality of sub-pixels arranged in a matrix, each sub-pixel of the plurality of sub-pixels comprising:
a substrate; a gate, a source and a drain, and a common electrode on the substrate; a passivation layer on a side of the common electrode facing away from the substrate; and a pixel electrode on a side of the passivation layer facing away from the substrate, wherein the array substrate further comprises a common electrode line, the common electrode line comprising a same material in a same layer as the source and the drain, wherein the common electrode is in direct electrical contact with the common electrode line, and wherein the pixel electrode and the drain are electrically connected through a via hole in the passivation layer.

2 . The array substrate according to claim 1 , wherein the common electrode overlaps at least a portion of the common electrode line.

3 . The array substrate according to claim 1 , further comprising:
a plurality of gate lines extending in a first direction and a plurality of data lines extending in a second direction, wherein each of the gate lines is electrically connected to gates of a plurality of sub-pixels arranged in the first direction, and wherein each of the data lines is electrically connected to sources of a plurality of sub-pixels arranged in the second direction; and a shielding line, wherein an orthographic projection of the shielding line on the substrate overlaps orthographic projections of one or more of the gate lines and the data lines on the substrate.

4 . The array substrate according to claim 3 , wherein the shielding line comprises a same material in a same layer as the pixel electrode.

5 . The array substrate according to claim 3 , wherein the shielding line is electrically connected to the common electrode line.

6 . The array substrate according to claim 1 ,
wherein the array substrate comprises a plurality of common electrode lines extending in parallel, wherein each of the plurality of common electrode lines is electrically connected to common electrodes of a plurality of sub-pixels arranged in an extension direction of the common electrode line, and wherein the array substrate further comprises a peripheral area surrounding a display area, wherein the peripheral area is provided with a common electrode auxiliary line, wherein the common electrode auxiliary line is electrically connected to the plurality of common electrode lines.

7 . The array substrate according to claim 6 , further comprising:
a plurality of gate lines extending in a first direction and a plurality of data lines extending in a second direction, wherein each of the gate lines is electrically connected to gates of a plurality of sub-pixels arranged in the first direction, and wherein each of the data lines is electrically connected to sources of a plurality of sub-pixels arranged in the second direction; and a shielding line, wherein an orthographic projection of the shielding line on the substrate overlaps orthographic projections of one or more of the gate lines and the data lines on the substrate, wherein the plurality of data lines are parallel to the plurality of common electrode lines, and wherein the common electrode auxiliary line is electrically connected to the shielding line.

8 . The array substrate according to claim 1 ,
wherein the pixel electrode comprises a first slit electrode, and wherein the common electrode comprises one of a platelike electrode and a second slit electrode.

9 . A display panel comprising the array substrate according to claim 1 .

10 . The display panel according to claim 9 , wherein the common electrode overlaps at least a portion of the common electrode line.

11 . The display panel according to claim 9 , further comprising:
a plurality of gate lines extending in a first direction and a plurality of data lines extending in a second direction, wherein each of the gate lines is electrically connected to gates of a plurality of sub-pixels arranged in the first direction, and wherein each of the data lines is electrically connected to sources of a plurality of sub-pixels arranged in the second direction; and a shielding line, wherein an orthographic projection of the shielding line on the substrate overlaps orthographic projections of one or more of the gate lines and the data lines on the substrate.

12 . The display panel according to claim 11 , wherein the shielding line is formed of a same material in a same layer as the pixel electrode.

13 . The display panel according to claim 11 , wherein the shielding line is electrically connected to the common electrode line.

14 . The display panel according to claim 9 ,
wherein the array substrate comprises a plurality of common electrode lines extending in parallel, wherein each of the plurality of common electrode lines is electrically connected to common electrodes of a plurality of sub-pixels arranged in an extension direction of the common electrode line, wherein the array substrate further comprises a peripheral area surrounding a display area, the peripheral area being provided with a common electrode auxiliary line, and wherein the common electrode auxiliary line is electrically connected to the plurality of common electrode lines.

15 . The display panel according to claim 14 , further comprising:
a plurality of gate lines extending in a first direction and a plurality of data lines extending in a second direction, wherein each of the gate lines is electrically connected to gates of a plurality of sub-pixels arranged in the first direction, and wherein each of the data lines is electrically connected to sources of a plurality of sub-pixels arranged in the second direction; and a shielding line, wherein an orthographic projection of the shielding line on the substrate overlaps orthographic projections of one or more of the gate lines and the data lines on the substrate, wherein the plurality of data lines are parallel to the plurality of common electrode lines, and wherein the common electrode auxiliary line is electrically connected to the shielding line.

16 . The display panel according to claim 9 ,
wherein the pixel electrode comprises a first slit electrode, and wherein the common electrode comprises one of a platelike electrode and a second slit electrode.

17 . A method for manufacturing an array substrate, comprising:
forming a gate, a source and a drain, and a common electrode on a substrate; forming a passivation layer on a side of the common electrode facing away from the substrate; forming a pixel electrode on a side of the passivation layer facing away from the substrate; and forming a common electrode line, wherein the common electrode line is formed by a same patterning process as the source and the drain, wherein the common electrode is in direct electrical contact with the common electrode line, and wherein the pixel electrode and the drain are electrically connected through a via hole in the passivation layer.

18 . The method for manufacturing the array substrate according to claim s 17 , wherein the common electrode overlaps at least a portion of the common electrode line.

19 . The method for manufacturing the array substrate according to claim 17 , further comprising:
forming a plurality of gate lines extending in a first direction and a plurality of data lines extending in a second direction; and forming a shielding line such that an orthographic projection of the shielding line on the substra

Assignees

• Boe Technology Group Co Ltd

Inventors

• Choi Hyunsic

Classifications

• G02F2201/123

  pixel · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/134363

  for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS] · CPC title

• G02F1/134309

  characterised by their geometrical arrangement · CPC title

• G02F2201/50

  Protective arrangements · CPC title