Capacitor unit and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2020143992-A1
Application number	US-201916518927-A
Country	US
Kind code	A1
Filing date	Jul 22, 2019
Priority date	Nov 5, 2018
Publication date	May 7, 2020
Grant date	—

Abstract

A capacitor unit and a manufacturing method thereof, which mainly include a substrate, an isolation layer formed on the substrate, and capacitor stacked structures located on the isolation layer to form a capacitor integrated structure including the capacitor units, are provided. Therefore, the capacitor integrated structure can be cut to form a plurality of the capacitor units that can function as capacitors, thereby simplifying the capacitor manufacturing process and reducing the manufacturing cost.

First claim

What is claimed is:

1 . A method of manufacturing a capacitor unit, comprising:
providing a substrate; forming an isolation layer on the substrate; forming a first capacitor stacked structure and a second capacitor stacked structure on the isolation layer; forming electrode connectors on the first capacitor stacked structure and the second capacitor stacked structure, wherein the electrode connectors are exposed, so that the electrode connectors, the first capacitor stacked structure, the second capacitor stacked structure, the isolation layer, and the substrate are combined to form a capacitor integrated structure, wherein the isolation layer electrically isolates the substrate from the first capacitor stacked structure and the second capacitor stacked structure; and cutting the capacitor integrated structure to form a first capacitor unit and a second capacitor unit separated from each other, wherein the first capacitor unit comprises two of the electrode connectors, the first capacitor stacked structure, a portion of the isolation layer, and a portion of the substrate, and the second capacitor unit comprises another two of the electrode connectors, the second capacitor stacked structure, another portion of the isolation layer, and another portion of the substrate.

2 . The method of manufacturing the capacitor unit according to claim 1 , wherein the step of forming the first capacitor stacked structure and the second capacitor stacked structure comprises:
forming a first conductive layer on the isolation layer; forming a capacitor dielectric layer on the first conductive layer; forming a second conductive layer on the capacitor dielectric layer; lithographically etching the second conductive layer, the capacitor dielectric layer, and the first conductive layer thereunder in sequence to expose a first portion of the capacitor dielectric layer and a first portion of the isolation layer; forming an interlayer dielectric layer to cover the second conductive layer, the first portion of the capacitor dielectric layer, and the first portion of the isolation layer; etching the interlayer dielectric layer to form first via holes and second via holes, wherein each of the first via holes passes through the first portion of the capacitor dielectric layer to expose the first conductive layer under the first portion of the capacitor dielectric layer, and each of the second via holes exposes the second conductive layer; respectively filling the first via holes and the second via holes with a metal material to form first metal pillars and second metal pillars; and forming a first bonding pad over the first metal pillars, and forming a second bonding pad over the second metal pillars, wherein the first bonding pad is electrically connected to the first conductive layer by the first metal pillars to form a first electrode, and the second bonding pad is electrically connected to the second conductive layer by the second metal pillars to form a second electrode.

3 . The method of manufacturing the capacitor unit according to claim 1 , wherein the step of forming the first capacitor stacked structure and the second capacitor stacked structure comprises:
forming a first conductive layer on the isolation layer; lithographically etching the first conductive layer to expose a first portion of the isolation layer; forming two spacers connected to two sidewalls of the first conductive layer; forming a capacitor dielectric layer covering the first conductive layer and the first portion of the isolation layer, wherein the capacitor dielectric layer comprises a third portion directly formed above the first portion of the isolation layer, and the capacitor dielectric layer and the sidewalls of the first conductive layer are isolated by the two spacers; forming a second conductive layer on a portion of the capacitor dielectric layer and exposing a fourth portion of the capacitor dielectric layer above the first conductive layer; forming an interlayer dielectric layer to cover the second conductive layer and the fourth portion of the capacitor dielectric layer; etching the interlayer dielectric layer to form first via holes and second via holes, wherein each of the first via holes passes through the fourth portion of the capacitor dielectric layer to expose the first conductive layer under the fourth portion, and each of the second via holes is disposed above the third portion of the capacitor dielectric layer to expose the second conductive layer above the third portion; respectively filling the first via holes and the second via holes with a metal material to form first metal pillars and second metal pillars; forming a bonding pad metal layer to respectively cover the interlayer dielectric layer, the first metal pillars, and the second metal pillars; and etching the bonding pad metal layer to form a first bonding pad over the first metal pillars and form a second bonding pad above the second metal pillars, wherein the first bonding pad is electrically connected to the first conductive layer by the first metal pillars to form a first electrode, and the second bonding pad is electrically connected to the second conductive layer by the second metal pillars to form a second electrode.

4 . The method of manufacturing the capacitor unit according to claim 1 , wherein the step of forming the first capacitor stacked structure and the second capacitor stacked structure comprises:
forming a first capacitor dielectric structure on the isolation layer, wherein the first capacitor dielectric structure comprises a first conductive layer formed on the isolation layer and a first capacitor dielectric layer formed on the first conductive layer, the first conductive layer comprises a first left electrode and a first right electrode isolated from each other, and the first capacitor dielectric layer comprises first left openings formed above the first left electrode and first right openings formed above the first right electrode; forming at least one second capacitor dielectric structure on the first capacitor dielectric structure, wherein the at least one second capacitor dielectric structure comprises a second conductive layer formed on the first capacitor dielectric layer and a second capacitor dielectric layer formed on the second conductive layer, the second conductive layer comprises a second left electrode and a second right electrode isolated from each other, the second left electrode is electrically connected to the first left electrode through the first left openings, the second right electrode is electrically connected to the first right electrode through the first right openings, the second capacitor dielectric layer comprises second left openings formed above the second left electrode and second right openings formed above the second right electrode, the second left openings and the first left openings are offset from each other, and the second right openings and the first right openings are offset from each other; forming a third conductive layer on the at least one second capacitor dielectric structure, wherein the third conductive layer comprises a third left electrode and a third right electrode isolated from each other, the third left electrode is electrically connected to the second left electrode through the second left openings, and the third right electrode is electrically connected to the second right electrode through the second right openings; forming a third interlayer dielectric layer to cover the third conductive layer, and planarizing a surface of the third interlayer dielectric layer; etching the third interlayer dielectric layer to form first via holes and second via holes, wherein each of the first via holes exposes an upper surface of the third left electrode, and each of the second via holes exposes an upper surface of the

Assignees

• Powerchip Semiconductor Mfg Corp

Inventors

• Lin Wei-Yu
• Cheng Shih-Hao

Classifications

• H05K1/181

  associated with surface mounted components · CPC title

• H05K2201/10015

  Non-printed capacitor · CPC title

• H01G4/306 Primary

  made by thin film techniques · CPC title

• H01L28/91

  Electricity · mapped topic

• H01L28/75

  Electricity · mapped topic