Power switch over current protection system

Patent metadata

Field	Value
Publication number	US-2020136601-A1
Application number	US-201816171012-A
Country	US
Kind code	A1
Filing date	Oct 25, 2018
Priority date	Oct 25, 2018
Publication date	Apr 30, 2020
Grant date	—

Abstract

A power switch over current protection system including a power switch transistor configured to deliver a power current from a power source to power load, a power switch driver configured to control and on/off state of the power switch, an over current protection (OCP) circuit to detect a threshold value of the power current, a discharge transistor configured to discharge a parasitic capacitance of the power switch transistor, and a system state machine to receive a signal from the OCP circuit configured to control an action of the power switch driver and discharge transistor depending on the level of the power current.

First claim

1 . A power switch over current protection system, comprising:
a power switch transistor configured to deliver a power current from a power source to power load; a power switch driver configured to control and on/off state of the power switch; an over current protection (OCP) circuit to detect a threshold value of the power current; a discharge transistor configured to discharge a parasitic capacitance of the power switch transistor; and a system state machine to receive a signal from the OCP circuit configured to control an action of the power switch driver and discharge transistor depending on the level of the power current.

2 . The system of claim 1 , wherein the OCP circuit triggers an over current event when the power current is higher than a predetermined threshold.

3 . The system of claim 1 , wherein the system state machine is configured to soft shut down the power switch transistor when the power current is higher than a predetermined threshold.

4 . The system of claim 3 , further comprising:
an electrostatic discharge (ESD) protection circuit disposed between the power source and the power switch transistor, wherein the soft shutting down of the power switch transistor protects the ESD protection circuit.

5 . The system of claim 1 , wherein the system state machine turns on the discharge transistor and turns off the power switch driver when the power current is higher than a predetermined threshold.

6 . The system of claim 5 , wherein the system state machine turns off the discharge transistor and turns on the power switch driver when the power current is lower than a predetermined threshold.

7 . The system of claim 1 , wherein the over current protection circuit is in parallel with the power switch transistor.

8 . The system of claim 1 , wherein the system state machine is in series with the over current protection circuit.

9 . The system of claim 1 , wherein the power switch transistor is an extended drain transistor.

10 . The system of claim 1 , wherein the discharge transistor is an extended drain transistor.

11 . The system of claim 1 , comprising a current mirror configured to isolate a gate voltage of the power switch transistor from an output voltage of the power switch transistor.

12 . The system of claim 11 , wherein one transistor of the current mirror is directly connected to the gate of the power switch transistor.

13 . A method, comprising:
detecting a charging current entering a power switch transistor; determining whether a level of the charging current exceeds a predetermined threshold; signaling to a system state machine by an over current protection circuit a status of the charging current; turning on a discharge transistor when the charging current exceeds the predetermined threshold; and soft shutting off a power switch transistor to protect electronic circuits that are connected to the power switch transistor.

14 . The method of claim 13 , wherein a decreasing rate of a gate voltage of the power switch transistor is calculated by the equation dV gate /dt=I discharge /C, where Idischarge is a discharge current, and C is a parasitic capacitance of the power switch transistor.

15 . The method of claim 13 , comprising switching on a discharge transistor while switching off a power switch driver that drives the power switch transistor.

16 . The method of claim 13 , comprising controlling an on state of a power switch transistor using a power switch driver.

17 . The method of claim 16 , comprising controlling an on state of the power switch driver using the system state driver.

18 . The method of claim 13 , wherein the protected electronic circuits include an ESD protection circuit.

19 . The method of claim 13 , wherein a gate voltage of the power switch transistor is isolated from an output voltage of the power switch transistor using a current mirror.

20 . The method of claim 13 , wherein the power switch transistor is configured to soft shut down in response to unplugging and plugging of a power cable to reduce kick back inductance in the power cable.

Assignees

• Nxp Bv

Inventors

• Liu Xiaoqun
• Vemula Madan Mohan Reddy

Classifications

• H03K17/0822 Primary

  in field-effect transistor switches · CPC title

• H02H9/02

  responsive to excess current {(current limitation for voltage regulators G05F1/573; disconnection after limiting H02H3/025)} · CPC title

• H03K17/08104

  in field-effect transistor switches (H03K17/0812, H03K17/0814 take precedence) · CPC title

• H03K17/687

  the devices being field-effect transistors · CPC title

• H03K17/693

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title