Techniques for monolithic co-integration of polycrystalline thin-film bulk acoustic resonator devices and monocrystalline iii-n semiconductor transistor devices

Patent metadata

Field	Value
Publication number	US-2020119087-A1
Application number	US-201616304965-A
Country	US
Kind code	A1
Filing date	Jul 1, 2016
Priority date	Jul 1, 2016
Publication date	Apr 16, 2020
Grant date	—

Abstract

Techniques are disclosed for monolithic co-integration of thin-film bulk acoustic resonator (TFBAR, also called FBAR) devices and III-N semiconductor transistor devices. In accordance with some embodiments, one or more TFBAR devices including a polycrystalline layer of a piezoelectric III-N semiconductor material may be formed alongside one or more III-N semiconductor transistor devices including a monocrystalline layer of III-N semiconductor material, over a commonly shared semiconductor substrate. In some embodiments, either (or both) the monocrystalline and the polycrystalline layers may include gallium nitride (GaN), for example. In accordance with some embodiments, the monocrystalline and polycrystalline layers may be formed simultaneously over the shared substrate, for instance, via an epitaxial or other suitable process. This simultaneous formation may simplify the overall fabrication process, realizing cost and time savings, at least in some instances.

First claim

1 . An integrated circuit comprising:
a substrate having a cavity therein; a transistor device over a first portion of the substrate and comprising a monocrystalline III-N semiconductor layer; and a resonator device over a second portion of the substrate such that the cavity extends under the resonator device, the resonator device comprising a polycrystalline piezoelectric III-N semiconductor layer.

2 . The integrated circuit of claim 1 , wherein the transistor device further comprises:
a polarization layer over the monocrystalline III-N semiconductor layer; a gate dielectric layer over the polarization layer; a gate layer over the gate dielectric layer; a source portion over a first region of the monocrystalline III-N semiconductor layer, adjacent the polarization layer; and a drain portion over a second region of the monocrystalline III-N semiconductor layer, adjacent the polarization layer.

3 . The integrated circuit of claim 2 , wherein the polarization layer comprises either:
aluminum indium nitride (Al x In 1-x N), wherein x is in the range of 0.7-0.99; aluminum gallium nitride (Al x Ga 1-x N), wherein x is in the range of 0.05-0.5; or aluminum indium gallium nitride (Al x In y Ga 1-x-y N), wherein x is in the range of 0.01-0.9 and y is in the range of 0.01-0.1.

4 . The integrated circuit of claim 2 , wherein at least one of the source portion and the drain portion comprises nitrogen and at least one of gallium and indium, and wherein at least one of the source portion and the drain portion is doped with at least one of silicon (Si) and germanium (Ge).

5 . The integrated circuit of claim 2 , wherein the transistor device further comprises:
a first contact over the source portion; and a second contact over the drain portion.

6 . The integrated circuit of claim 5 , wherein the transistor device further comprises:
a first electrode over the first contact; and a second electrode over the second contact.

7 . The integrated circuit of claim 1 , wherein the resonator device further comprises at least one of:
a first electrode on a first side of the polycrystalline piezoelectric III-N semiconductor layer; and a second electrode on a second side of the polycrystalline piezoelectric III-N semiconductor layer.

8 . The integrated circuit of claim 7 , wherein at least one of the first electrode and the second electrode comprises at least one of tungsten (W), molybdenum (Mo), tantalum nitride (TaN), and titanium nitride (TiN).

9 . The integrated circuit of claim 1 , further comprising at least one of:
a dielectric layer over the substrate, laterally adjacent to the cavity; and a dielectric layer over the polycrystalline piezoelectric III-N semiconductor layer and extending into the cavity.

10 . A method of fabricating an integrated circuit, the method comprising:
forming a transistor device over a first portion of a substrate, the substrate comprising semiconductor material, and the transistor device comprising a monocrystalline III-N semiconductor layer; forming a resonator device over a second portion of the substrate, the resonator device comprising a polycrystalline piezoelectric III-N semiconductor layer; and forming a cavity within the substrate, wherein the cavity extends under the resonator device.

11 . The method of claim 10 , wherein forming the transistor device comprises:
forming a first layer over the monocrystalline III-N semiconductor layer; forming a second layer over the first layer; forming a third layer over the second layer; forming a source portion over a first region of the monocrystalline III-N semiconductor layer, adjacent the first layer; and forming a drain portion over a second region of the monocrystalline III-N semiconductor layer, adjacent the first layer; wherein the first layer comprises either
aluminum indium nitride (Al x In 1-x N) with x in the range of 0.7-0.99;
aluminum gallium nitride (Al x Ga 1-x N) with x in the range of 0.05-0.5; or
aluminum indium gallium nitride (Al x In y Ga 1-x-y N) with x in the range of 0.01-0.9 and y in the range of 0.01-0.1;
wherein the second layer comprises a gate dielectric material; and wherein the third layer comprises a gate electrode material.

12 . (canceled)

13 . (canceled)

14 . (canceled)

15 . (canceled)

16 . (canceled)

17 . (canceled)

18 . The method of claim 10 , further comprising at least one of:
forming a fourth layer over the substrate, laterally adjacent to the cavity, the fourth layer comprising a dielectric material; and forming a fifth layer over the polycrystalline piezoelectric III-N semiconductor layer and extending into the cavity, the fifth layer comprising a dielectric material.

19 . An integrated circuit comprising:
a substrate; a transistor device over a first portion of the substrate and comprising a monocrystalline gallium nitride (GaN) layer; and a acoustic resonator device over a second portion of the substrate, the acoustic resonator device comprising a polycrystalline GaN layer.

20 . The integrated circuit of claim 19 , wherein the transistor device further comprises:
a polarization layer over the monocrystalline GaN layer; a gate dielectric layer over the polarization layer; a gate layer over the gate dielectric layer; a drain portion over a first region of the monocrystalline GaN layer, adjacent the polarization layer; and a source portion over a second region of the monocrystalline GaN layer, adjacent the polarization layer.

21 . The integrated circuit of claim 19 , wherein the acoustic resonator device further comprises:
a first electrode on a first side of the polycrystalline GaN layer; and a second electrode on a second side of the polycrystalline GaN layer; wherein at least one of the first electrode and the second electrode comprises an electrically conductive refractory material.

22 . The integrated circuit of claim 19 , wherein the substrate comprises a Group IV semiconductor material.

23 . The integrated circuit of claim 19 , wherein the substrate comprises a Group III-V compound semiconductor material.

24 . A radio frequency (RF) filter circuit comprising the integrated circuit of claim 19 .

25 . A mobile computing device comprising the RF filter circuit of claim 24 .

26 . The integrated circuit of claim 2 , wherein the polarization layer comprises aluminum, nitrogen and one or both of gallium and indium.

Assignees

• Intel Corp

Inventors

• Then Han Wui
• Radosavljevic Marko
• Dasgupta Sansaptak
• Fischer Paul B
• Gardner Sanaz K
• Block Bruce A

Classifications

• H10P14/3416

  Nitrides · CPC title

• H03H9/0542 Primary

  consisting of a lateral arrangement (H03H9/0566 takes precedence) · CPC title

• H03H2003/021

  the resonators or networks being of the air-gap type · CPC title

• H03H9/545

  including active elements · CPC title

• H03H9/173

  Air-gaps · CPC title