Multi-pitch ball grid array

Patent metadata

Field	Value
Publication number	US-2020105650-A1
Application number	US-201816146993-A
Country	US
Kind code	A1
Filing date	Sep 28, 2018
Priority date	Sep 28, 2018
Publication date	Apr 2, 2020
Grant date	—

Abstract

A mixed pitch method of placing pads in a ball grid array (BGA) package having a. BGA substrate and a plurality of connectors arranged in an array and connected via the pads to the BGA substrate. Selected pairs of the pads are placed on the BGA substrate at a distance defined by a first pitch PT. Ground pads are placed on the BGA substrate at a distance from the selected pairs of pads defined by a second pitch P 2, K wherein P 2 =M*P 1 and M is greater than one. The selected pairs of the pads on the BGA substrate are also placed at a distance from other selected pairs of the pads defined by the second pitch P 2.

First claim

What is claimed is:

1 . In a ball grid array (BGA) package having a BGA substrate and a plurality of connectors arranged in an array and connected via signal pads and ground pads to the BGA substrate, a method comprising:
placing selected pairs of the signal pads on the BGA substrate at a distance defined by a first pitch P 1 ; placing selected ground pads on the BGA substrate at a distance from adjacent selected pairs of signal pads defined by a second pitch P 2 , wherein P 2 =M*P 1 and M is greater than one; and placing the selected pairs of the signal pads on the BGA substrate at a distance from adjacent selected pairs of the signal pads defined by the second pitch P 2 .

2 . The method of claim 1 .hereirr the connectors include solder balls.

3 . The method of claim 1 , wherein the connectors are further connected through power pads to the BGA substrate, the method further comprising:
placing selected power and ground pads of the BGA substrate at distances apart defined by a third pitch P 3 , wherein P 3 =N*P 1 , wherein 0<N<1.

4 . The method of claim 3 , wherein the selected power pads include VDD pads.

5 . The method of claim 3 , wherein N=1/M.

6 . The method of claim 3 , further comprising placing one or more of the ground pads at distances from one or more signal pads defined by the third pitch.

7 . The method of claim 1 , wherein portions of the array are arranged as rows and columns of connectors, with pairs of signal pads placed in adjacent rows in the same column, the method further comprising:
separating columns of the connectors in the array as a function of the second pitch and separating rows of the connectors in the array that do not include one of the pairs of signal pads as a function of the second pitch.

8 . A component, comprising:
a ball grid array package (BGA); and an integrated circuit, wherein the BGA package includes a BGA substrate and an array of BGA connectors, a plurality of pads on the BGA substrate attached to the integrated circuit and a plurality of BGA pads deposited as an array on a side the BGA substrate opposite the pads attached to the integrated circuit and connected to the BGA connectors, wherein the BGA connectors include BGA signal connectors and BGA ground connectors, wherein selected pairs of the BGA signal connectors are placed on the BGA package at a distance defined by a first pitch PT, wherein selected BGA ground connectors are placed on the BGA package at a distance from adjacent selected pairs of BGA connectors defined by a second pitch P 2 , wherein P 2 =M*P 1 and M is greater than one, and wherein the selected pairs of BGA signal connectors on the BGA package are separated from adjacent selected pairs of BGA signal connectors on the BGA package by a distance defined by the second pitch.

9 . The component of claim 8 , wherein the plurality of BGA connectors further include VDD connectors, wherein selected BGA ground connectors on the BGA package are separated from adjacent VDD connectors on the BGA package by a third pitch P 3 , P 3 =N*P 1 , wherein 0<N<1.

10 . The component of claim 8 , wherein portions of the array of BGA connectors on the BGA package are arranged as rows and columns of BGA connectors, with pairs of BGA signal connectors placed in adjacent rows in the same column,
wherein columns of the BGA connectors in the array of BGA connectors are separated as a function of the second pitch, wherein rows of the BGA connectors that do include a signal connector that is one of the selected pairs of signal connectors are separated as a function of the first pitch and wherein rows of the BGA connectors that do not include a BGA signal connector that is one of the selected pairs of signal connectors are separated as a function of the second pitch.

11 . The component of claim 8 , wherein the array of connectors includes solder balls.

12 . The component of claim 8 , wherein the first pitch is 1.0 mm and the second pitch is 1.25 mm.

13 . A printed circuit board (PCB), comprising:
a plurality of layers, including a top layer; and. a plurality of pads disposed on the top layer, wherein the plurality of pads are distributed on the top layer in a pattern matching a mixed pitch ball grid array of connectors on a corresponding ball grid array (BGA) package, wherein the plurality of pads includes signal pads and ground pads, wherein selected pairs of signal pads on the top layer are separated by a distance defined by a first pitch, wherein selected ground pads are separated by a distance defined by a second pitch from adjacent selected pairs of signal pads, wherein P 2 =M*P 1 and M is greater than one, and wherein the selected pairs of signal pads are separated from adjacent selected pairs of signal pads by a distance defined by the second pitch.

14 . The PCB of claim 13 , wherein the PCB further comprises ground vias located in spaces on the PCB created by separating the selected pairs of signal pads from adjacent ground pads by a distance defined by the second pitch.

15 . The PCB of claim 13 , wherein the mixed pitch ball grid array of pads further include VDD pads, wherein selected ground pads are separated from adjacent VDD pads by a third pitch P 3 , P 3 =N*P 1 , wherein 0<N<1.

16 . The PCB of claim 15 , wherein the PCB further comprises ground vias located in spaces on the PCB created by separating the selected pairs of signal pads from adjacent ground pads by a distance defined by the second pitch.

17 . The PCB of claim 13 , wherein a portion of the pads located on the top layer are arranged as rows and columns of pads, with pairs of signal pads placed in adjacent rows in the same column,
wherein columns of the pads are separated as a function of the second pitch, wherein rows of the pads that do include a signal pad that is one of the selected pairs of signal pads are separated as a function of the first pitch and wherein rows of the pads that do not include a signal pad that is one of the selected pairs of signal pads are separated as a function of the second pitch.

18 . The PCB of claim 17 , wherein the PCB further comprises ground vias located in spaces on the PCB created by separating the selected pairs of signal pads from adjacent ground pads by a distance defined by the second pitch.

19 . The PCB of claim 17 , wherein the PCB further comprises antipads in areas of the PCB where spaces were created by separating the selected pairs of signal pads from adjacent ground pads by the second pitch that are larger than antipads in other areas of the PCB.

20 . The PCB of claim 19 , wherein the signal pads are coupled to the antipads.

Assignees

• Juniper Networks Inc

Inventors

• Rangaswamy Granthana Kattehalli
• Hanumantharayappa Arvind
• Venkataraman Srinivas

Classifications

• H05K2201/10734

  Ball grid array [BGA]; Bump grid array · CPC title

• H05K3/3436

  having an array of bottom contacts, e.g. pad grid array or ball grid array components · CPC title

• H05K1/113

  Via provided in pad; Pad over filled via · CPC title

• H01L23/49816 Primary

  Electricity · mapped topic

• H01L24/17

  Electricity · mapped topic