Super-junction semiconductor device fabrication

Patent metadata

Field	Value
Publication number	US-2020105529-A1
Application number	US-201816228356-A
Country	US
Kind code	A1
Filing date	Dec 20, 2018
Priority date	Sep 28, 2018
Publication date	Apr 2, 2020
Grant date	—

Abstract

To manufacture a super-junction (SJ) layer of a SJ device, an epitaxial (epi) layer having a first conductivity type may be formed on an underlying layer, which may be formed from a wide-bandgap material. A first mask may then be formed onto a first portion of the epi layer, and a first set of SJ pillars may be selectively implanted into a second portion of the epi layer exposed by the first mask. Then, a second mask may be formed on the second portion of the epi layer that is self-aligned relative to the first mask. After removing the first mask, a second set of SJ pillars may be selectively implanted into the first portion of the epi layer. Removing the second mask may then yield the SJ layer.

First claim

1 . A method of manufacturing a super-junction (SJ) layer of a SJ device, comprising:
forming a first epitaxial (epi) layer having a first conductivity type on an underlying layer, wherein the underlying layer is formed from a wide-bandgap material; forming a first mask by disposing a first material on a first portion and a second portion of the first epi layer and then patterning the first material to selectively expose the second portion of the first epi layer; selectively implanting a first set of SJ pillars having the first conductivity type into the exposed second portion of the first epi layer; forming a second mask by disposing a second material different from the first material on the second portion of the first epi layer, wherein the second mask is self-aligned relative to the first mask; removing the first mask to expose the first portion of the first epi layer without exposing the second portion of the first epi layer; selectively implanting a second set of SJ pillars having a second conductivity type into the exposed first portion of the first epi layer; and removing the second mask to yield the SJ layer.

2 . The method of claim 1 , comprising:
forming a second epi layer having the first conductivity type on the SJ layer, wherein the second epi layer is formed from the wide-bandgap material; forming the first mask by disposing the first material on a first portion and a second portion of the second epi layer and then patterning the first material to selectively expose the second portion of the second epi layer; selectively implanting the first set of SJ pillars into the second portion of the second epi layer; forming the second mask by disposing the second material on the second portion of the second epi layer, wherein the second mask is self-aligned relative to the first mask on the second epi layer; removing the first mask to expose the first portion of the second epi layer without exposing the second portion of the second epi layer; selectively implanting the second set of SJ pillars having the second conductivity type into the exposed first portion of the second epi layer; and removing the second mask to yield an additional SJ layer.

3 . The method of claim 2 , wherein implanting the first set of SJ pillars into the second portion of the second epi layer comprises implanting the first set of SJ pillars to extend through an entire thickness of the second epi layer and contact the first set of SJ pillars of the first epi layer.

4 . The method of claim 1 , wherein implanting the first set of SJ pillars comprises implanting using implantation energies equal to or greater than approximately 0.1 mega-electron volts (MeV).

5 . The method of claim 4 , wherein the implantation energies are less than approximately 50 MeV.

6 . The method of claim 1 , wherein implanting the first set of SJ pillars comprises implanting to a depth equal to or greater than approximately 5 microns (μm).

7 . The method of claim 6 , wherein the depth is equal to or less than approximately 15 μm.

8 . The method of claim 1 , wherein implanting the first set of SJ pillars comprises implanting the first set of SJ pillars to extend through a thickness of the first epi layer and contact the underlying layer.

9 . The method of claim 1 , wherein the first epi layer comprises silicon carbide (SiC).

10 . The method of claim 1 , comprising forming the first epi layer with a doping concentration approximately less than 5×10 15 per centimeter cubed (cm −3 ).

11 . The method of claim 10 , wherein the doping concentration is approximately greater than or equal to 1×10 14 cm −3 .

12 . The method of claim 1 , wherein the first set of SJ pillars comprises a doping concentration between approximately 5×10 15 cm −3 and approximately 1×10 17 cm −3 .

13 . The method of claim 1 , wherein the underlying layer comprises a semiconductor substrate layer, a second epi layer, an additional SJ layer, or a combination thereof.

14 . The method of claim 1 , comprising forming a device layer having the first conductivity type above the SJ layer to yield a super-junction (SJ) semiconductor device, wherein the SJ semiconductor device comprises a metal-oxide-semiconductor field-effect transistor (MOSFET), a junction field effect transistor (JFET), a bipolar junction transistor (BJTs), or a diode.

15 . A super-junction (SJ) semiconductor device intermediate, comprising:
an epitaxial (epi) layer having a first conductivity type, wherein the epi layer comprises a wide-bandgap material, wherein a first portion of the epi layer comprises a plurality of implanted super-junction (SJ) pillars having a second conductivity type; a first high energy implantation mask disposed directly above the first portion of the epi layer, wherein the first high energy implantation mask comprises a first material; and a second high energy implantation mask disposed self-aligned relative to the first high energy implantation mask directly above a second portion of the epi layer, wherein the second high energy implantation mask comprises a second material different from the first material, wherein the second portion of the epi layer is not covered by the first high energy implantation mask.

16 . The SJ semiconductor device intermediate of claim 15 , wherein when a removal technique is applied to the SJ semiconductor device intermediate, the first high energy implantation mask is configured to be removed based at least in part on the first material and the second high energy implantation mask is configured to remain effective based at least in part on a chemical difference, a physical difference, or a combination thereof between the first high energy implantation mask and the second high energy implantation mask.

17 . The SJ semiconductor device intermediate of claim 15 , wherein the first high energy implantation mask and the second high energy implantation mask independently comprise a different one or more of silicon oxide, silicon nitride, polycrystalline silicon, silicon, a metal layer, or a resist layer.

18 . A method, comprising:
A) forming an epitaxial (epi) layer having a first conductivity type on an underlying layer, wherein the underlying layer is formed from a wide-bandgap material; B) forming a first mask comprising a first material disposed on a first portion of the epi layer, wherein a second portion of the epi layer is exposed by the first mask; C) selectively implanting a first set of super-junction (SJ) pillars having a second conductivity type into the second portion of the epi layer; D) forming a second mask comprising a second material disposed on the second portion of the epi layer, wherein the second mask is self-aligned relative to the first mask and the second material is different from the first material; E) removing the first mask to expose the first portion of the epi layer without exposing the second portion of the epi layer; F) selectively implanting a second set of SJ pillars having the first conductivity type into the exposed first portion of the epi layer; G) removing the second mask to yield a super-junction (SJ) layer; and H) forming a device layer having the first conductivity type above the SJ layer to yield a super-junction (SJ) semiconductor device.

19 . The method of claim 18 , comprising, prior to step H, repeating steps A-G at least once to form an additional SJ layer.

20 . The method of claim 18 , wherein forming the epi layer comprises growing the epi layer directly on the underlying layer.

Assignees

• Gen Electric

Inventors

• Ghandi Reza
• Bolotnikov Alexander Viktorovich
• Losee Peter Almern
• Lilienfeld David Alan

Classifications

• H10D12/032

  of vertical IGBTs · CPC title

• H10P30/22 Primary

  using masks · CPC title

• H01L29/0634

  Electricity · mapped topic

• H01L21/0465 Primary

  Electricity · mapped topic

• H10D62/054

  by high energy implantations in bulk semiconductor bodies, e.g. forming pillars · CPC title