Hot carrier injection fuse memory

Patent metadata

Field	Value
Publication number	US-2020105356-A1
Application number	US-201816147119-A
Country	US
Kind code	A1
Filing date	Sep 28, 2018
Priority date	Sep 28, 2018
Publication date	Apr 2, 2020
Grant date	—

Abstract

Memory cell circuitry is disclosed. The memory cell circuitry includes a first transistor configured to have a threshold voltage of the first transistor modulated by hot carrier injection, a second transistor coupled to the first transistor and configured to have a threshold voltage of the second transistor modulated by hot carrier injection, a word line coupled to a gate of the first transistor and to a gate of the second transistor, a first bit line coupled to the first transistor and a second bit line coupled to the second transistor. In addition, the memory cell circuitry includes a source line coupled to the drain of the first transistor and to the drain of the second transistor, the word line and the source line configured to cause hot carrier injection (HCI) into the first transistor when a first supply voltage is applied to the word line and the source line, and the second bit line is floated and the first bit line is grounded. The word line and the source line are configured to cause hot carrier injection into the second transistor when the first supply voltage is applied to the word line and the source line, and the first bit line is floated and the second bit line is grounded. Methods utilizing this technology for generating a multi-time programmable non-volatile memory and a random number generator for physical unclonable function applications are included in this disclosure.

First claim

What is claimed is:

1 . Memory cell circuitry, comprising:
a first transistor configured to have a threshold voltage of the first transistor modulated by hot carrier injection; a second transistor coupled to the first transistor and configured to have a threshold voltage of the second transistor modulated by hot carrier injection; a word line coupled to a gate of the first transistor and to a gate of the second transistor; a first bit line coupled to the first transistor and a second bit line coupled to the second transistor; and a source line coupled to the drain of the first transistor and to the drain of the second transistor, the word line and the source line configured to cause hot carrier injection (HCI) into the first transistor when a first supply voltage is applied to the word line and the source line, and the second bit line is floated and the first bit line is grounded, and into the second transistor when a first supply voltage is applied to the word line and the source line, and the first bit line is floated and the second bit line is grounded.

2 . The memory cell circuitry of claim 1 , further comprising a sense amplifier configured to access a differential voltage from the first bit line and the second bit line in response to a second supply voltage being applied to the word line and to the source line.

3 . The memory cell circuitry of claim 1 , further comprising a bit cell that includes the first transistor and the second transistor and is an HCI fuse bit cell.

4 . The memory cell circuitry of claim 1 , wherein the hot carrier injection into the first transistor causes Vt degradation of the first transistor and the hot carrier injection into the second transistor causes Vt degradation of the second transistor.

5 . The memory cell circuitry of claim 4 , wherein the Vt degradation of the first transistor causes the storage of a first logic level.

6 . The memory cell circuitry of claim 4 , wherein the Vt degradation of the second transistor causes the storage of a second logic level.

7 . The memory cell circuitry of claim 3 , wherein the un-programmed bit cell contains a random value that is used to generate a random key for physical unclonable function (PUF) applications.

8 . A memory cell array, comprising:
input and output circuitry; and a plurality of memory cells that include: a first transistor configured to have a threshold voltage of the first transistor modulated by hot carrier injection; a second transistor coupled to the first transistor and configured to have a threshold voltage of the second transistor modulated by hot carrier injection; a word line coupled to a gate of the first transistor and to a gate of the second transistor; a first bit line coupled to the first transistor and a second bit line coupled to the second transistor; and a source line coupled to the drain of the first transistor and to the drain of the second transistor, the word line and the source line configured to cause hot carrier injection (HCI) into the first transistor when a first supply voltage is applied to the word line and the source line, and the second bit line is floated and the first bit line is grounded, and into the second transistor when a first supply voltage is applied to the word line and the source line, and the first bit line is floated and the second bit line is grounded.

9 . The memory cell array of claim 8 , further comprising a sense amplifier configured to access a differential voltage from the first bit line and the second bit line in response to a second supply voltage being applied to the word line and to the source line.

10 . The memory cell array of claim 8 , further comprising a bit cell that includes the first transistor and the second transistor and is an HCI bit cell fuse.

11 . The memory cell array of claim 8 , wherein hot carrier injection into the first transistor causes Vt degradation of the first transistor and hot carrier injection into the second transistor causes Vt degradation of the second transistor.

12 . The memory cell array of claim 11 , wherein the Vt degradation of the first transistor causes the storage of a first logic level.

13 . The memory cell array of claim 11 , wherein the Vt degradation of the second transistor causes the storage of a second logic level.

14 . The memory cell array of claim 10 , wherein the un-programmed bit cell contains a random value that is used to generate a random key for physical unclonable function (PUF) applications.

15 . A method, comprising:
programming a memory cell of memory cell array, including: applying a first program voltage to a gate of a first transistor of the memory cell and to a gate of a second transistor of the memory cell for a first duration that causes a first shift in the threshold voltage of the first transistor; and responsive to the applying the first program voltage, providing access to a differential signal that includes voltages that correspond to a bit line of the first transistor and a bit line of the second transistor; causing a first reset of the memory cell, including: applying a second program voltage to the gate of the first transistor and to the gate of the second transistor for a second duration that causes a first shift in the threshold voltage of the second transistor that is at least twice the magnitude of the first shift in the threshold voltage of the first transistor; and responsive to the applying the second program voltage, providing access to a differential signal that includes voltages from the bit line of the first transistor and from the bit line of the second transistor; causing a second reset of the memory cell, including: applying a third program voltage to the gate of the first transistor and to the gate of the second transistor for a third duration that causes a second shift in the threshold voltage of the first transistor that is at least three times the magnitude of the first shift in the threshold voltage of the first transistor; and responsive to the applying the third program voltage, providing access to a third differential signal that includes voltages that correspond to the bit line of the first transistor and the bit line of the second transistor.

16 . The method of claim 15 , wherein the programming is from an initial un-programmed state of the memory cell present at fabrication.

17 . The method of claim 16 , wherein the initial un-programmed state of the memory cell includes a random value.

18 . The method of claim 15 , wherein the memory cell is an HCI fuse bit-cell.

19 . The method of claim 15 , wherein the memory cell array is an HCI fuse array.

20 . The method of claim 15 , wherein the memory cell array can be used to generate a random key for PUF applications.

Assignees

• Intel Corp

Inventors

• Kulkarni Sarvesh
• Dorgan Vincent
• Meric Inanc
• Vangara Venkata Krishna Rao
• Bhattacharya Uddalak
• Hicks Jeffrey

Classifications

• G11C17/16 Primary

  using electrically-fusible links · CPC title

• G11C17/18 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title

• H04L9/3278

  using physically unclonable functions [PUF] · CPC title