Magnetic recording array and magnetic recording device

Patent metadata

Field	Value
Publication number	US-2020105310-A1
Application number	US-201916292959-A
Country	US
Kind code	A1
Filing date	Mar 5, 2019
Priority date	Sep 28, 2018
Publication date	Apr 2, 2020
Grant date	—

Abstract

A magnetic recording array includes: a plurality of domain wall moving elements; a first wiring which is electrically connected to a reference potential and is electrically connected to at least one domain wall moving element of the plurality of domain wall moving elements; a second wiring which is electrically connected to at least two or more domain wall moving elements of the plurality of domain wall moving elements; a first switching element which is connected between each of the domain wall moving elements and the first wiring; and a second switching element which is connected between each of the domain wall moving elements and the second wiring, wherein an OFF resistance of the first switching element is smaller than an OFF resistance of the second switching element.

First claim

1 . A magnetic recording array comprising:
a plurality of domain wall moving elements; a first wiring which is electrically connected to a reference potential and is electrically connected to at least one domain wall moving element of the plurality of domain wall moving elements; a second wiring which is electrically connected to at least two or more domain wall moving elements of the plurality of domain wall moving elements; a first switching element which is connected between each of the domain wall moving elements and the first wiring; and a second switching element which is connected between each of the domain wall moving elements and the second wiring, wherein each of the domain wall moving elements includes a magnetic recording layer which is electrically connected to the first wiring and the second wiring and includes a magnetic domain wall, a first ferromagnetic layer, and a non-magnetic layer which is located between the first ferromagnetic layer and the magnetic recording layer, wherein an OFF resistance of the first switching element is smaller than an OFF resistance of the second switching element, and wherein a resistance area product (RA) of the domain wall moving element is 1×10 5 Ωμm 2 or more.

2 . The magnetic recording array according to claim 1 ,
wherein the OFF resistance of the first switching element is smaller than a resistance value of the non-magnetic layer.

3 . The magnetic recording array according to claim 1 ,
wherein the first wiring is grounded.

4 . The magnetic recording array according to claim 1 , further comprising:
a substrate which supports the first switching element and the second switching element and is exposed to an outside, wherein the first wiring is electrically connected to the substrate.

5 . The magnetic recording array according to claim 1 ,
wherein the first switching element and the second switching element are transistors.

6 . A magnetic recording array comprising:
a plurality of domain wall moving elements; a first wiring which is electrically connected to a reference potential and is electrically connected to at least one domain wall moving element of the plurality of domain wall moving elements; a second wiring which is electrically connected to at least two or more domain wall moving elements of the plurality of domain wall moving elements; a first switching element which is connected between each of the domain wall moving elements and the first wiring; and a second switching element which is connected between each of the domain wall moving elements and the second wiring, wherein each of the domain wall moving elements includes a magnetic recording layer which is electrically connected to the first wiring and the second wiring and includes a magnetic domain wall, a first ferromagnetic layer, and a non-magnetic layer which is located between the first ferromagnetic layer and the magnetic recording layer, wherein an OFF resistance of the first switching element is smaller than an OFF resistance of the second switching element, and wherein the OFF resistance of the first switching element is smaller than a resistance value of the non-magnetic layer.

7 . The magnetic recording array according to claim 6 ,
wherein the first wiring is grounded.

8 . The magnetic recording array according to claim 7 , further comprising:
a substrate which supports the first switching element and the second switching element and is exposed to the outside, wherein the first wiring is electrically connected to the substrate.

9 . The magnetic recording array according to claim 7 ,
wherein the first switching element and the second switching element are transistors.

10 . A magnetic recording device comprising:
first memory element and second memory element each of which includes a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer interposed between the first ferromagnetic layer and the second ferromagnetic layer; a first switching element which is electrically connected to at least one second ferromagnetic layer of one of the first memory element and the second memory element; a first conductive portion which is electrically connected to the first switching element and a predetermined potential; a second switching element which is electrically connected to the second ferromagnetic layers of both of the first memory element and the second memory element, an electric resistance thereof in an OFF state being higher than an electric resistance of the first switching element; and a second conductive portion which is electrically connected to the second switching element, wherein a resistance area product of the first memory element is 1×10 5 Ωμm 2 or more, and wherein a resistance area product of the second memory element is 1×10 5 Ωμm 2 or more.

11 . The magnetic recording device according to claim 10 ,
wherein the first switching element and the second switching element are transistors.

12 . The magnetic recording device according to claim 11 ,
wherein the first switching element and the second switching element are formed in a semiconductor layer, and each of the first memory element and second memory element is formed on each of insulation layer formed on the first switching element and the second switching element.

Assignees

• Tdk Corp

Inventors

• Ashida Takuya
• Shibata Tatsuo

Classifications

• G11C11/1659 Primary

  Cell access · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C5/08 Primary

  for interconnecting magnetic elements, e.g. toroidal cores · CPC title

• H01L27/228

  Electricity · mapped topic

• H01L27/224

  Electricity · mapped topic