Memory system and operating method thereof

Patent metadata

Field	Value
Publication number	US-2020104073-A1
Application number	US-201916406233-A
Country	US
Kind code	A1
Filing date	May 8, 2019
Priority date	Sep 28, 2018
Publication date	Apr 2, 2020
Grant date	—

Abstract

A memory system includes a memory device including a plurality of normal memory blocks and a plurality of dummy memory blocks; and a controller suitable for controlling the memory device, wherein the controller includes: a memory suitable for temporarily storing user data corresponding to a write command; and a processor suitable for performing a one-shot program operation of programming the user data into an open memory block in the memory device by comparing a size of the user data with a reference size for the one-shot program operation.

First claim

What is claimed is:

1 . A memory system comprising:
a memory device including a plurality of normal memory blocks and a plurality of dummy memory blocks; and a controller suitable for controlling the memory device, wherein the controller includes:
a memory suitable for storing user data corresponding to a write command; and
a processor suitable for performing a one-shot program operation of programming the user data into an open memory block in the memory device by comparing a size of the user data with a reference size for the one-shot program operation.

2 . The memory system of claim 1 , wherein the processor programs the user data into a normal open memory block among the plurality of normal memory blocks when the size of the user data is equal to the reference size.

3 . The memory system of claim 1 , wherein the processor programs the user data into a dummy open memory block among the plurality of dummy memory blocks when the size of the user data is different from the reference size.

4 . The memory system of claim 3 , wherein the processor selects a type of a target open memory block to which the user data is to be programmed, and subsequently compares the reference size corresponding to the type of the memory block with the size of the user data.

5 . The memory system of claim 4 , wherein, when the target open memory block is a single level cell memory block, the processor determines a size of a physical page as the reference size and compares the size of the physical page with the size of the user data.

6 . The memory system of claim 4 , wherein, when the target open memory block is a multiple level cell memory block, the processor determines a total size of a plurality of logical pages corresponding to one physical page as the reference size, and compares the total size of the logical pages with the size of the user data.

7 . The memory system of claim 1 ,
wherein the memory stores the number of valid pages included in each of the normal memory backs and the dummy memory blocks under the control of the processor, wherein the processor retrieves a victim block based on the number of valid pages, copies valid data stored in the victim block, and programs the valid data into the open memory block.

8 . The memory system of claim 7 , wherein the processor retrieves the victim block when the memory device is in an idle state.

9 . The memory system of claim 7 , wherein the processor retrieves the victim block from the plurality of dummy memory blocks.

10 . The memory system of claim 9 , wherein the processor retrieves the victim block from the plurality of normal memory blocks when the victim block is not retrieved from the plurality of dummy memory blocks.

11 . An operating method for a memory system including a plurality of normal memory blocks and a plurality of dummy memory blocks, the operating method comprising:
storing user data corresponding to a write command; comparing a size of the user data with a reference size for a one-shot program operation; and performing the one-shot program operation of programming the user data into an open memory block based on the comparison result.

12 . The operating method of claim 11 , wherein the user data is programmed into a normal open memory block among the plurality of normal memory blocks when the size of the user data is equal to the reference size.

13 . The operating method of claim 11 , wherein the user data is programmed into a dummy open memory block among the plurality of dummy memory blocks when the size of the user data is different from the reference size.

14 . The operating method of claim 13 ,
further comprising selecting a type of a target open memory block to which the user data is to be programmed, wherein the size of the user data is compared with the reference size corresponding to the type of the memory block.

15 . The operating method of claim 14 , wherein, when the target open memory block is a single level cell memory block, the reference size is a size of a physical page.

16 . The operating method of claim 14 , wherein, when the target open memory block is a multiple level cell memory block, the reference size is a total size of a plurality of logical pages corresponding to one physical page.

17 . The operating method of claim 11 , further comprising:
storing the number of valid pages included in each of the normal memory bucks and the dummy memory blocks; retrieving a victim block based on the number of valid pages; copying valid data stored in the victim block; and programming the valid data into the open memory block.

18 . The operating method of claim 17 , wherein the victim block is retrieved when a memory device is in an idle state.

19 . The operating method of claim 17 , wherein the victim block is retrieved from the plurality of dummy memory blocks.

20 . The operating method of claim 19 , wherein the victim block is retrieved from the plurality of normal memory blocks when the victim block is not retrieved from the plurality of dummy memory blocks.

Assignees

• Sk Hynix Inc

Inventors

• Byun Eu-Joon

Classifications

• G06F3/064 Primary

  Management of blocks · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F3/0673

  Single storage device · CPC title